X9271_14 Datasheet, PDF (2/18 Pages) Intersil Corporation – Single, Digitally Controlled Potentiometer

X9271
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
V_CC LIMITS POTENTIOMETER TEMP. RANGE
MARKING
(V)
ORGANIZATION (kΩ)
(°C)
PACKAGE
Pb-Free
PKG.
DWG. #
X9271UV14IZ (Note 1)
X9271 UVZI 5 ±10%
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z (Note 1)
X9271 UVZ
5 ±10%
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7
X9271 UVZG 2.7 to 5.5
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7T1
X9271 UVZG 2.7 to 5.5
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7
X9271 UVZF 2.7 to 5.5
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7T1
X9271 UVZF 2.7 to 5.5
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
Pin Configuration
X9271
14 LD TSSOP
TOP VIEW
S0
1
A0
2
NC
3
CS
4
SCK
5
SI
6
V_SS
7
14
V_CC
13
R_L
12
R_H
11
R_W
10
HOLD
9
A1
8
WP
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN NAME
SO
A0
NC
CS
SCK
SI
V_SS
WP
A1
HOLD
R_W
R_H
R_L
V_CC
Serial Data Output
Device Address
No Connect
Chip Select
Serial Clock
Serial Data Input
System Ground
Hardware Write Protect
Device Address
Device Select. Pause the serial bus.
Wiper Terminal of Potentiometer
High Terminal of Potentiometer
Low Terminal of Potentiometer
System Supply Voltage
FUNCTION
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2
FN8174.4
July 18, 2014