X9271_14 Datasheet, PDF (6/18 Pages) Intersil Corporation – Single, Digitally Controlled Potentiometer

X9271
.
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to
store wiper positions or data (Nonvolatile, NV)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NV NV NV NV NV NV NV NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
WIP
(LSB)
Device Description
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bit is the device ID for the X9271;
this is fixed as 0101[B] (Table 4).
The A1 - A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the A1
- A0 input pins. The slave address is externally specified by
the user. The X9271 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9271 to successfully
continue the command sequence. Only the device for which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 - A0 inputs can
be actively driven by CMOS input signals or tied to V_CC or
V_SS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction operation code (I[3:0]).
The RB and RA bits point to one of the four Data Registers.
P0 is the POT selection; since the X9271 is single POT,
P0 = 0. The format is shown in Table 7.
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks. Bank 0 is
the default bank of registers. Only Bank 0 registers can be
used for the data register to Wiper Counter Register
operations.
Banks 1, 2, and 3 are additional banks of registers (12 total)
that can be used for SPI write and read operations. The data
registers in Banks 1, 2, and 3 cannot be used for direct
read/write operations to the Wiper Counter Register
(Tables 5 and 6).
TABLE 4. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
SET TO 0 FOR
PROPER
OPERATION
INTERNAL
SLAVE
ADDRESS
ID3 ID2 ID1 ID0
0
0
A1
A0
0
1
0
1
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3)
REGISTER
RB RA SELECTION
OPERATIONS
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write; Wiper
Counter Register Operations
1
0
2
Data Register Read and Write; Wiper
Counter Register Operations
1
1
3
Data Register Read and Write; Wiper
Counter Register Operations
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
BANK
P1 P0 SELECTION
OPERATIONS
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write Only
1
0
2
Data Register Read and Write Only
1
1
3
Data Register Read and Write Only
INSTRUCTION OPCODE
I3
I2
I1
P0
(MSB)
NOTE:
4. Set to P0 = 0 for potentiometer operations.
TABLE 7. INSTRUCTION BYTE FORMAT
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
REGISTER
SELECTION
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 4)
RB
RA
P1
P0
(LSB)
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FN8174.4
July 18, 2014