ISL76534 Datasheet, PDF (7/24 Pages) Intersil Corporation – 14-channel gamma references

ISL76534
Electrical Specifications A_VDD = A_VDD_AMP = 15V, D_VDD = 3.3V, REF_IN = 14.75V, T_A = +25°C, unless otherwise specified. Boldface limits
apply across the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6)
TYP
(Note 6) UNIT
Power Supply Rejection Ratio
DAC Integral Non-Linearity
PSRR
OUT1-OUT14: OUTx = 0.5*A_VDD
A_VDD varied from 14V to 16V
55
75
OUTCOM: OUTCOM = 0.5*A_VDD
50
70
A_VDD_AMP varied from 14V to 16V
INL
DAC1 through DAC14
-2
0
dB
dB
2
LSB
DAC15 (OUTCOM)
-2
0
2
LSB
Input Leakage Current of REF_IN
Input Leakage Current of V_COM
Amplifier
I_{L_REF}
I_{L_INN}
REF_IN = 0.5*A_VDD
V_COM Amplifier: INN = 0.5*A_VDD
-1
0
1
µA
-1
0
1
µA
Short-Circuit Current
I_SC
OUT1-OUT14: OUTx = V_OH, OUTx short to
170
230
400
mA
GND (source) through 10Ω
OUT1-OUT14: OUTx = V_OL, OUTx short to
150
200
400
mA
A_VDD (sink) through 10Ω
V_COM Amplifier (OUTCOM):
400
530
700
mA
OUTx = 0.5*A_VDD_AMP, short to GND
(source) through 10Ω
Load Regulation
Slew Rate
V_COM Amplifier (OUTCOM):
OUTx = 0.5*A_VDD_AMP, short to
A_VDD_AMP (sink) through 10Ω
REG
OUT1-OUT14: I_LOAD = ±5mA step
OUTCOM: I_LOAD = ±5mA step
SR
OUT1-OUT14: Full-scale DAC code
change
450
570
750
mA
0
1.5
5
mV/mA
0
1.5
5
mV/mA
2
5
40
V/µs
V_COM amplifier: A_V = -1,
4
0.5V ≤ OUTx ≤ 5.5V, C_L = 10pF to GND
V_COM Amplifier Bandwidth
BW
A_V = -1, OUTx = 4V,
R_L = 10kΩ || C_L = 10pF to GND
Time to Load EEPROM Data to DAC t_{Data_loading} Start of EEPROM loading to when OUTx is
Registers at Power-ON
enabled, (Note 7)
10
40
V/µs
5
MHz
6
ms
DIGITAL
Logic ‘1’ Input Voltage
V_IH
SCL, SDA, A0, WP
0.8*D_VDD
Logic ‘0’ Input Voltage
I²C SCL Clock Frequency
V_IL
SCL, SDA, A0, WP
f_CLK
(Note 8)
Input Leakage Current
I_L
SCL, SDA, A0, WP: at GND
-1
0
SCL, SDA: at D_VDD
-1
0
A0, WP: at D_VDD
0.10
0.55
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The “t_{Data_loading}” parameter is determined by IC design, and simulation.
8. For more detailed information regarding I²C timing characteristics, refer to Table 1 on page 13.
V
0.2 * D_VDD
V
400
kHz
1
µA
1
µA
1
µA
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FN8866.0
July 27, 2016