ISL76534 Datasheet, PDF (21/24 Pages) Intersil Corporation – 14-channel gamma references

ISL76534
UVLO and Output Enable
The ISL76534 includes an Undervoltage Lock-Out (UVLO) for
A_VDD. At power-ON the output drivers, OUTx and OUTCOM, are
initially in a high impedance (disabled) state, A_VDD < UVLO.
The OUT1-OUT14 outputs are ENABLED when the internal
EEPROM recall has been completed (see “Recalling The
EEPROM” on page 20), and A_VDD rises above 4.5V (maximum).
Although OUTCOM is powered from A_VDD_AMP, it is internally
linked to the A_VDD UVLO function. The OUTCOM will be enabled
when A_VDD and A_VDD_AMP rise above 4.5V (maximum).
The OUT1-OUT14 and OUTCOM outputs are DISABLED if A_VDD
falls below 3.5V (minimum).
Power Sequencing
The ISL76534 has no restrictions on power supply sequencing of
A_VDD and D_VDD. A_VDD_AMP should not exceed A_VDD. A_VDD_AMP
can also be set to GND to disable the function.
The DAC reference, REF_IN, voltage should not exceed A_VDD. This
ensures the ESD protection diodes from REF_IN to A_VDD do not
become forward biased. If REF_IN does exceed A_VDD, then the
current flow through the ESD diode should not exceed 10mA.
Thermal Shutdown
The ISL76534 features thermal shutdown, which protects the
device from damage due to overheating. When the junction (die)
temperature rises to 160°C (typical) all outputs, OUTx and
OUTCOM, are disabled (high-impedance). When the die
temperature cools by 20°C (typical) all outputs are re-enabled.
Power Dissipation
With high short-circuit and continuous output current capability
for each channel, it is possible to exceed the +150°C absolute
maximum junction (die) temperature. Therefore, it is important
to calculate the maximum junction temperature for the
application to determine if load or circuit conditions need to be
modified to keep the device in a safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
P_DMAX
=
T_{----J---M-----A----X-----–-----}T_{---A----M-----A----X--}
_JA
(EQ. 3)
Where:
• T_JMAX = Maximum junction temperature
• T_AMAX = Maximum ambient temperature
• _JA = Thermal resistance of the package
• P_DMAX = Maximum power dissipation in the package
For more details on the allowable package power dissipation,
refer to Figures 23 and 24.
Power Supply Bypassing and Printed Circuit
Board Layout
Good Printed Circuit Board (PCB) layout is necessary for optimum
performance. The following are recommendations to achieve
optimum high frequency performance from your PCB.
• To optimize thermal performance, solder the ISL76534’s
exposed thermal pad to GND. PCB vias should be placed below
the device’s exposed thermal pad and connected to GND to
transfer heat away from the device (see “General PowerPAD
Design Considerations”). If the thermal pad is not connected to
GND then it should be electrically isolated.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e., no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
• When testing, use good quality connectors and cables, match
cable types and keep cable lengths to a minimum.
• A minimum of two power supply decoupling capacitors are
recommended (typically 4.7µF and 0.1µF) per supply and
placed as close to the IC as possible. Avoid placing vias
between the capacitor and the device because vias add
unwanted inductance. Larger value capacitors can be placed
farther away.
General PowerPAD Design
Considerations
Figure 29 is an example of how to use vias to distribute heat
away from an IC.
FIGURE 29. PCB VIA PATTERN
For optimal thermal performance, use vias to distribute heat
away from the IC and to a system power plane. Fill the thermal
pad area with vias that are spaced 3x their radius (typically),
center-to-center, from each other. The via diameters should be
kept small, but they should be large enough to allow solder
wicking during reflow. To optimize heat transfer efficiency, do not
connect vias using “thermal relief” patterns. Vias should be
directly connected to the plane with plated through-holes.
Connect all vias to the correct voltage potential (power plane)
indicated in the datasheet. For the ISL76534, the thermal pad
potential is ground (GND).
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FN8866.0
July 27, 2016