ISL76534 Datasheet, PDF (20/24 Pages) Intersil Corporation – 14-channel gamma references

ISL76534
Output Stability
The ISL76534 outputs are designed to drive capacitive loads,
such as in TFT-LCD panel. However, purely capacitive loads
should not exceed 1nF without appropriate external load
isolation and/or amplifier compensation.
As load capacitance increases, the -3dB bandwidth will decrease
and peaking can occur. Depending on the application, it may be
necessary to reduce peaking and improve device stability. To do
this, a snubber circuit (compensation) or a series resistor
(isolation) may be added to the output of the ISL76534.
A snubber is a shunt load consisting of a resistor in series with a
capacitor. An optimized snubber can improve the phase margin
and the stability of the ISL76534 by adding a zero in the loop
response. The advantage of a snubber circuit is that it does not
draw any DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Write Protection (WP)
The ISL76534 has an I²C write protection (WP) pin. WP is a logic
level input pin and is active low.
• WP = 0 (LOW): Protected, device ignores I²C data writes to the
internal DAC registers and EEPROM
• WP = 1 (HIGH): Not Protected, device allows I²C data writes to
the internal DAC registers and EEPROM
Whether WP is set HIGH or LOW, the device will ACK to proper I²C
commands, however, when WP = LOW the device internally
ignores the data bytes.
The logic state of WP can be changed during device operation.
However, WP should not be changed during the EEPROM write
procedure time.
Writing to the EEPROM
During an I²C transaction, setting bit b₁₄ of a Data Word HIGH
indicates to the device that the data in that same Data Word
should be written to both the DAC and EEPROM. The EEPROM
programming cycle for the appropriate channel(s) is started as
soon as a subsequent STOP command is issued on the I²C bus.
After the STOP condition is issued, it takes up to 35ms
(maximum) for a single EEPROM Register Write, and 420ms
(maximum) to write all registers to EEPROM. To ensure EEPROM
data validity, wait at least 35ms between single EEPROM
Register Writes, and before sending any other I²C commands.
When writing all registers to EEPROM, wait at least 420ms
before sending any other I²C commands. During the EEPROM
programming cycle time, the device's I²C bus is internally busy
and will NACK I²C commands.
Note, the normal DAC
quickly as the I²C bus
writes (bit b₁₄
can support.
=
‘0’)
can
be
written
to
as
OUT1-OUT14 AND OUTCOM BEHAVIOR
During the EEPROM writing/programming cycle the ISL76534
gamma outputs (OUT1-OUT14) and V_COM amplifier output
(OUTCOM) remain enabled.
Recalling The EEPROM
There are two ways to initiate a recall of the stored EEPROM data:
• Automatic recall - Power cycle (or power-ON) the device
• Manual recall - Perform a “software reset” using I²C
The recall operation will overwrite all current DAC register values
with the values stored in EEPROM.
AUTOMATIC RECALL
When the device is powered-ON, the ISL76534 automatically
recalls the EEPROM data and loads it into the DAC registers
(RAM) after D_VDD reaches ~2.2V. The time for the EEPROM recall
to complete is the “t_{Data_loading}” time and is 6ms (typical) by
design. This operation restores all DAC registers to the values
stored in EEPROM.
MANUAL RECALL
A recall can be initiated by performing a software reset using I²C.
A software reset is done by writing data 0x06 to Register Pointer
0x00 (Control Byte), and then on the falling edge of 8^th SCL clock
(of the Control Byte), the recall operation will be started. The
device will then issue a NACK on the 9^th SCL clock.
Recalling the ISL76534 EEPROM data to the output DACs takes
6ms typical) to complete. During the EEPROM recall time
(power-ON or during a software reset), OUT1-OUT14 and OUTCOM
will be set to high impedance and the device will NACK to any I²C
commands. Once the EEPROM recall is complete OUT1-OUT14
and OUTCOM will enable simultaneously and the outputs will
slew to the correct level. If some or all of the outputs
(OUT1-OUT14, OUTCOM) need to be defined (not high impedance)
during this delay time, an external resistor divider may be used to
set a “coarse” voltage until the DAC outputs are enabled.
Note, the ISL76534 EEPROM values are pre-programmed to the
default values explained in the “DEFAULT EEPROM VALUES”
section.
EEPROM Default Values
The ISL76534 has factory programmed (default) EEPROM values
for the output channels, which will be recalled from EEPROM and
loaded to the DAC registers at initial power-ON. The default
EEPROM values are shown in Table 6.
DAC #
DAC1-14
DAC15
TABLE 6. DEFAULT EEPROM VALUES
CHANNEL CODE (hex)
EXPECTED OUTPUT
VOLTAGE (V)
OUT1-14
0x000
GND
OUTCOM
0x200
REF_IN/2
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July 27, 2016