ISL76534 Datasheet, PDF (12/24 Pages) Intersil Corporation – 14-channel gamma references

ISL76534
General Description
The Voltage/Transmission (V/T) transfer curve or gamma curve
of LCD panels require adjustment to achieve the desired optimal
visual response (often called gamma correction).
The ISL76534 has a total of 15 channels (14xgamma channels +
1xV_{COM channel}) independent, programmable reference voltage
outputs whose output voltage can be set with 10-bit resolution. The
ISL76534 has integrated EEPROM to store all gamma and V_COM
data.
In addition to the 14-channel gamma DACs, the ISL76534
provides a V_COM calibrator DAC with 10-bit resolution and a high
output current operational amplifier to drive the V_COM voltage
also required by the LCD panel.
I²C Digital Interface
The ISL76534 uses a standard I²C interface bus for
communication. The two-wire interface links a master(s) and
uniquely addressable slave devices. The master generates clock
signals and is responsible for initiating data transfers. The serial
clock is on the SCL line and the serial data (bidirectional) is on
the SDA line. The ISL76534 supports clock rates up to 400kHz
(fast-mode), and is backwards compatible with standard 100kHz
clock rates (standard-mode).
The SDA and SCL lines must be HIGH when the bus if free - not in
use. An external pull-up resistor (typically 2.2kΩto4.7kΩ) or
current source is required for SDA and SCL.
The ISL76534 meets standard I²C timing specifications; see
Figure 25 and Table 1, which show the standard timing
definitions and specifications for I²C communication.
Data Validity
The data on the SDA line must be stable (clearly defined as HIGH
or LOW) during the HIGH period of the clock signal. The state of
the SDA line can only change when the SCL line is low (except to
create a START or STOP condition). See timing specifications on
Table 1 on page 13.
The voltage levels used to indicate a logical ‘0’ (LOW) and logical
‘1’ (HIGH) are determined by the V_IL and V_IH thresholds,
respectively; see the “Electrical Specifications” table on page 6.
START and STOP Condition
All I²C communication begins with a START condition, indicating
the beginning of a transaction, and ends with a STOP condition,
signaling the end of the transaction.
A START condition is signified by a HIGH to LOW transition on the
Serial Data line (SDA) while the Serial Clock Line (SCL) is HIGH. A
STOP condition is signified by a LOW to HIGH transition on the
SDA line while SCL is HIGH. See timing specifications in Table 1.
The master always initiates START and STOP conditions. After a
START condition, the bus is considered “busy.” After a STOP
condition, the bus is considered “free.” The ISL76534 also
supports repeated STARTs, where the bus will remain busy for
continued transaction(s).
Byte Format
Every byte on the SDA must be 8 bits in length. After every byte of
data sent by the transmitter, there must be an acknowledge bit
(from the receiver) to signify that the previous 8 bits were
transferred successfully. Data is always transferred on the SDA
with the Most Significant Bit (MSB) first. If the data is larger than
8 bits then it can be separated into multiple 8-bit bytes. See
“Data Word (WRITE/READ)” on page 19.
Acknowledge (ACK)
Each 8-bit data transfer is followed by an Acknowledge (ACK) bit
from the receiver. The Acknowledge bit signifies that the previous
8 bits of data was transferred successfully (master-slave or
slave-master).
When the master sends data to the slave (e.g. during a WRITE
transaction), after the 8^th bit of a data byte is transmitted, the
master tri-states the SDA line during the 9^th clock. The slave
device acknowledges that it received all 8 bits by pulling down
the SDA line, generating an ACK bit.
When the master receives data from the slave (e.g. during a data
READ transaction), after the 8^th bit is transmitted, the slave tri-states
the SDA line during the 9^th clock. The master acknowledges that it
received all 8 bits by pulling down the SDA line, generating an ACK bit.
V_IH
SDA
V_IL
t_SU:STA
V_IH
SCL
V_IL
t_HD:STA
t_r
t_r
t_f
t_f
t_BUF
t_SU:STO
START
t_SU:DAT
t_HD:DAT
FIGURE 25. I²C TIMING DEFINITIONS
STOP START
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July 27, 2016