ISL76534 Datasheet, PDF (13/24 Pages) Intersil Corporation – 14-channel gamma references

ISL76534
TABLE 1. I²C TIMING CHARACTERISTICS
FAST-MODE
PARAMETER
SYMBOL
MIN
MAX
SCL Clock Frequency
Set-Up Time for a START Condition
Hold Time for a START Condition
Set-Up Time for a STOP Condition
Bus Free Time between a STOP and START Condition
Data Set-Up Time
Data Hold Time
Rise Time of SDA and SCL (Note 9)
Fall Time of SDA and SCL (Note 9)
NOTE:
9. C_b = total capacitance of one bus line in pF
f_SCL
0
400
t_SU:STA
0.6
t_HD:STA
0.6
t_SU:STO
0.6
t_BUF
1.3
t_SU:DAT
100
t_HD:DAT
0
t_r
20 + 0.1C_b
300
t_f
20 + 0.1C_b
300
STANDARD-MODE
MIN
MAX
0
100
4.7
4.0
4.0
4.7
250
0
1000
300
UNIT
kHz
µs
µs
µs
µs
ns
µs
ns
ns
Not Acknowledge (NACK)
A Not Acknowledge (NACK) is generated when the receiver does
not pull down the SDA line during the acknowledge clock (i.e.,
SDA line remains HIGH during the 9^th clock). This indicates to the
master that it can generate a STOP condition to end the
transaction and free the bus.
A NACK can be generated for various reasons, for example:
• After an I²C device address is transmitted, there is NO receiver
with that address on the bus to respond.
• The receiver is busy performing an internal operation (e.g.
reset, recall, etc.), and cannot respond.
• The master (acting as a receiver) needs to indicate the end of a
transfer with the slave (acting as a transmitter).
Device Address and R/W Bit
Data transfers follow the format shown in Figures 26 through 27.
After a valid START condition, the first byte sent in a transaction
contains the 7-bit device (slave) Address plus a direction (R/W)
bit. The Device Address identifies which device (of up to 127
devices on the I²C bus) the master wishes to communicate with.
After a START condition, the ISL76534 monitors the first 8 bits
(Device Address byte) and checks for it is 7-bit Device Address in
the MSBs. If it recognizes the correct Device Address it will ACK,
and becomes ready for further communication. If it does not see
it is Device Address, it will sit idle until another START condition is
issued on the bus.
To access the ISL76534 DACs, the Device Addresses allowed are
0x74 hex (1110100x), or 0x75 hex (1110101x). The first 6 bits (b₇
to b₂, MSBs) of the 7-bit device address have been factory
programmed and are always 111010. Only the least significant bit
of the Device Address (bit b₁, LSB) is allowed to change. The value of
the LSB (bit b₁) is set by the hardware “A0” pin. When A0 = HIGH,
the device will only respond to a Device Address of 0x75. When
A0 = LOW, the device will only respond to a Device Address of 0x74.
This allows for two ISL76534 devices to be used on the same I²C
bus, each with a different Device Address.
Note: The eighth bit of the Device Address byte (bit b₀) indicates
the direction of transfer, READ or WRITE (R/W). A “0” indicates a
WRITE operation- the master will transmit data to the ISL76534
(receiver). A “1” indicates a Read operation- the master will
receive data from the ISL76534 (transmitter).
Application Information
ISL76534 Communication Protocol
The ISL76534 allows the user to sequentially read or write all the
registers with a single multi-byte I²C READ or WRITE operation
(“Burst Mode”).
The ISL76534 also allows the user to READ or WRITE to a specific
register only (or a specific range of registers), using Register Pointer
addressing (“Register Mode”). With Register Mode, a specific V_COM
value, Gamma DAC value or range of values may be read or written
without having to read or write the other registers.
Register Description and Pointer
Table 2 contains a detailed register description. All registers
contain 10 bits, which span over two data bytes (16 bits) and the
data is latched-in after the 16^th bit (LSB) is received. The only
exception is the Control Register, where the data is latched in
after the first 8 bits are received.
Reading/writing always begins at location specified by the Register
Pointer. The Register Pointer automatically increments by 0x01 with
every two bytes transferred. For example, when using Register
Pointer 0x01 to address DAC1 (MSB and LSB), the device
automatically increments the pointer to 0x02, 0x03... after every
two data bytes are received. This enables Burst Mode operation
where only the first Register Pointer for a given sequence of
registers is needed.
To address separate or non-sequential register locations, a full
I²C START, Device Address, Register Pointer, Data..., STOP
sequence must be used to address each register location; see
“WRITE TRANSACTION” on page 15.
The Control Register is located at Register Pointer 0x00, while
the 10-bit DAC data is at Register Pointers 0x01 though 0x0F.
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FN8866.0
July 27, 2016