ISL62873 Datasheet, PDF (7/17 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62873
Electrical Specifications
These specifications apply for T_A = -10°C to +100°C, unless otherwise stated.
All typical specifications T_A = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
OTP Rising Threshold Temperature
(Note 2)
T_OTRTH
-
150
-
°C
OTP Hysteresis (Note 2)
T_OTHYS
NOTE:
2. Limits established by characterization and are not production tested.
-
25
-
°C
Functional Pin Descriptions
GND (Pin 1)
IC ground for bias supply and signal reference.
EN (Pin 2)
Enable input for the IC. Pulling EN above the V_ENTHR rising
threshold voltage initializes the soft-start sequence.
VID0 (Pin 3)
Logic input for setpoint voltage selector. Use to select
between the two setpoint reference voltages. External
reference input when enabled by connecting the SET0 pin to
the VCC pin.
SREF (Pin 4)
Soft-start and voltage slew-rate programming capacitor
input. Setpoint reference voltage programming resistor input.
Connects internally to the inverting input of the V_SET voltage
setpoint amplifier. See Figure 5 on page 9 for capacitor and
resistor connections.
SET0 (Pin 5)
Voltage set-point programming resistor input. See Figure 5
on page 9 for resistor connection.
PGOOD (Pin 6)
Power-good open-drain indicator output. This pin changes to
high impedance when the converter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
has shut down the regulator. See Table 2 on page 12.
FB (Pin 7)
Voltage feedback sense input. Connects internally to the
inverting input of the control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 9 on page 13.
VO (Pin 8)
Output voltage sense input for the R³ modulator. The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 6 on page 10.
OCSET (Pin 9)
Input for the overcurrent detection circuit. The overcurrent
setpoint programming resistor R_OCSET connects from this
pin to the sense node. See Figure 6 on page 10.
PHASE (Pin 10)
Return current path for the UGATE high-side MOSFET
driver. V_IN sense input for the R³ modulator. Inductor current
polarity detector input. Connect to junction of output inductor,
high-side MOSFET, and low-side MOSFET. See “Application
Schematics” (Figures 2 and 3) on page 3.
UGATE (Pin 11)
High-side MOSFET gate driver output. Connect to the gate
terminal of the high-side MOSFET of the converter.
BOOT (Pin 12)
Positive input supply for the UGATE high-side MOSFET gate
driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC
between the BOOT pin and the PHASE pin.
VCC (Pin 13)
Input for the IC bias voltage. Connect +5V to the VCC pin
and decouple with at least a 1µF MLCC to the GND pin. See
“Application Schematics” (Figures 2 and 3) on page 3.
PVCC (Pin 14)
Input for the LGATE and UGATE MOSFET driver circuits.
The PVCC pin is internally connected to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin
and decouple with a 10µF MLCC to the PGND pin. See
“Application Schematics” (Figures 2 and 3) on page 3.
LGATE (Pin 15)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 16)
Return current path for the LGATE MOSFET driver. Connect
to the source of the low-side MOSFET.
Setpoint Reference Voltage Programming
Voltage identification (VID) pins select user-programmed
setpoint reference voltages that appear at the SREF pin. The
converter is in regulation when the FB pin voltage (V_FB)
7
FN6930.0
June 30, 2009