ISL62873 Datasheet, PDF(16/17 Page) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

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ISL62873 Datasheet, PDF (16/17 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

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ISL62873

EN, PGOOD, VID0, and VID1 Pins

These are logic signals that are referenced to the GND pin.

Treat as a typical logic signal.

OCSET and VO Pins

The current-sensing network consisting of ROCSET, RO, and

CSEN needs to be connected to the inductor pads for

accurate measurement of the DCR voltage drop. These

components however, should be located physically close to

the OCSET and VO pins with traces leading back to the

inductor. It is critical that the traces are shielded by the

ground plane layer all the way to the inductor pads. The

procedure is the same for resistive current sense.

FB, SREF, SET0, SET1, and SET2 Pins

The input impedance of these pins is high, making it critical

to place the loop compensation components, setpoint

reference programming resistors, feedback voltage divider

resistors, and CSOFT close to the IC, keeping the length of

the traces short.

LGATE, PGND, UGATE, BOOT, and PHASE Pins

The signals going through these traces are high dv/dt and

high di/dt, with high peak charging and discharging current.

The PGND pin can only flow current from the gate-source

charge of the low-side MOSFETs when LGATE goes low.

Ideally, route the trace from the LGATE pin in parallel with

the trace from the PGND pin, route the trace from the

UGATE pin in parallel with the trace from the PHASE pin,

and route the trace from the BOOT pin in parallel with the

trace from the PHASE pin. These pairs of traces should be

short, wide, and away from other traces with high input

impedance; weak signal traces should not be in proximity

with these traces on any layer.

Copper Size for the Phase Node

The parasitic capacitance and parasitic inductance of the

phase node should be kept very low to minimize ringing. It is

best to limit the size of the PHASE node copper in strict

accordance with the current and thermal management of the

application. An MLCC should be connected directly across

the drain of the upper MOSFET and the source of the lower

MOSFET to suppress the turn-off voltage spike.

FN6930.0

June 30, 2009

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