ISL62873 Datasheet, PDF (15/17 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62873
1000
900
800
700
Q_U = 100nC
Q_L = 200nC
Q_U = 50nC
Q_L = 100nC
Q_U = 50nC
Q_L = 50nC
600
Q_U = 20nC
500
Q_L = 50nC
400
300
200
100
0
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 12. POWER DISSIPATION vs FREQUENCY
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V_DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
V_IN - V_OUT, plus the spike, across it. The preferred low-side
MOSFET emphasizes low r _DS(ON) when fully saturated to
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as Equation 31:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} ⋅ (1 – D)
(EQ. 31)
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 32:
P_{CON_HS}
=
I_LO
A
2
D
⋅
r_D
S
(
ON)_
H
S
⋅
D
(EQ. 32)
For the high-side MOSFET, its switching loss is written as
Equation 33:
P_{SW_HS}
=
V_{-----I--N-----}⋅_---I_{--V----A----L---L---E----Y-----}⋅_---t_{--O-----N-----}⋅_---F_{----S----W---}
2
+
-^V----^I--^N-----^â‹---^I--^P----^E----^A----^K-----^â‹---^t-^O-----^F----^F----^â‹---^F----^S----^W---
2
(EQ. 33)
Where:
- I_VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I_PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t_ON is the time required to drive the device into
saturation
- t_OFF is the time required to drive the device into cut-off
Layout Considerations
The IC, analog signals, and logic signals should all be on the
same side of the PCB, located away from powerful emission
sources. The power conversion components should be
arranged in a manner similar to the example in Figure 13
where the area enclosed by the current circulating through
the input capacitors, high-side MOSFETs, and low-side
MOSFETs is as small as possible and all located on the
same side of the PCB. The power components can be
located on either side of the PCB relative to the IC.
GND
++
OUTPUT
CAPACITORS
VOUT
PHASE
NODE
HIGH-SIDE
MOSFETS
VIN
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the bottom
setpoint-reference programming-resistor, bottom feedback
voltage-divider resistor (if used), and the CSOFT capacitor
be made as close as possible to the GND pin on a conductor
not shared by any other components.
In addition to the critical single point connection discussed in
the previous paragraph, the ground plane layer of the PCB
should have a single-point-connected island located under the
area encompassing the IC, setpoint reference programming
components, feedback voltage divider components,
compensation components, CSOFT capacitor, and the
interconnecting traces among the components and the IC. The
island should be connected using several filled vias to the rest
of the ground plane layer at one point that is not in the path of
either large static currents or high di/dt currents. The single
connection point should also be where the VCC decoupling
capacitor and the GND pin of the IC are connected.
Power Ground
Anywhere not within the analog-ground island is Power
Ground.
VCC and PVCC Pins
Place the decoupling capacitors as close as practical to the
IC. In particular, the PVCC decoupling capacitor should have
a very short and wide connection to the PGND pin. The VCC
decoupling capacitor should not share any vias with the
PVCC decoupling capacitor.
15
FN6930.0
June 30, 2009