ISL62873 Datasheet, PDF (13/17 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62873
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V. The dead-time shown in
Figure 8 is extended by the additional period that the falling
gate voltage remains above the 1V threshold. The high-side
gate-driver output voltage is measured across the UGATE
and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is supplied
by a boot-strap capacitor connected across the BOOT and
PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop below PVCC such as when
the low-side MOSFET is turned on.
Compensation Design
Figure 9 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C_INT is a 100pF capacitor
integrated inside the IC, connecting across the FB pin and the
COMP signal. R_FB, R_COMP, C_COMP and C_INT form the Type-II
compensator. The frequency domain transfer function is given
by Equation 21:
G_COMP(s)
=
-------------¹----+-----^s-----^â‹---⁽--^R-----^F---^B-----+-----^R-----^C----^O----^M-----^P----⁾----^â‹---^C----^C----^O-----^M-----^P--------------
s
⋅
R_F
B
⋅
C_I
N
T
⋅
(
1
+
s
⋅
R_COM
P
⋅
C
C
O
)
MP
(EQ. 21)
C_INT = 100pF
COMP
-
FB
EA
+
SREF
R_COMP
C_COMP
R_FB
R_OFS
V_OUT
FIGURE 9. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R³ modulator used in the
IC makes the LC output filter resemble a first order system in
which the closed loop stability can be achieved with the
recommended Type-II compensation network. Intersil provides
a PC-based tool that can be used to calculate compensation
network component values and help simulate the loop
frequency response.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
13
reference designs that include schematics, bills of materials,
and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is expressed
in Equation 22:
D
=
-^V-----^O---
V_IN
(EQ. 22)
The output inductor peak-to-peak ripple current is expressed
in Equation 23:
I_P-P
=
-^V----^O-----^â‹---⁽---¹-----–----^D-----⁾
F_SW ⋅ L
(EQ. 23)
A typical step-down DC/DC converter will have an I_P-P of
20% to 40% of the maximum DC output load current. The
value of I_P-P is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated using Equation 24:
P_COPPER
=
I_L
O
A
2
D
⋅
D
CR
(EQ. 24)
Where, I_LOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_P-P can flow. Current I_P-P develops
a corresponding ripple voltage V_P-P across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are expressed in
Equations 25 and 26:
ΔV_ESR = I_P-P ⋅ ESR
(EQ. 25)
ΔΔV_C = ₈-----_â‹---_C----^I-_O-^P---^---_â‹^P---_F---_S----_W----
(EQ. 26)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V_P-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered. A capacitor dissipates heat as
a function of RMS current and frequency. Be sure that I_P-P is
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at F_SW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
FN6930.0
June 30, 2009