HFA3842B Datasheet, PDF (7/26 Pages) Intersil Corporation – PCMCIA/USB Wireless LAN Medium Access Controller

HFA3842B
AC Electrical Specifications (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
SYSTEM INTERFACE - PC CARD IO READ 16
Data Delay After HIORD-
Data Hold Following HIORD-
HIORD- Width Time
Address Setup Before HIORD-
Address Hold Following HIORD-
HCE(1, 2)- Setup Before HIORD-
HCE(1, 2)- Hold After HIORD-
HREG- Setup Before HIORD-
HREG- Hold Following HIORD-
HINPACK- Delay Falling from HIORD-
HINPACK- Delay Rising from HIORD-
Data Delay from HWAIT- Rising
HWAIT- Width Time
SYSTEM INTERFACE - PC CARD IO WRITE 16
t_DIORD
-
t_HIORD
0
t_WIORD
165
t_SUA
70
t_HA
20
t_SUCE
5
t_HCE
20
t_SUREG
5
t_HREG
0
t_DFINPACK
0
d_DRINPACK
30
t_DRWT
-
t_WWT
-
-
100
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
45
ns
-
45
ns
-
0
ns
-
12,000
ns
Data Setup Before HIORD-
Data Hold Following HIORD-
HIOWR- Width Time
Address Setup Before HIORD-
Address Hold Following HIORD-
HCE(1, 2)- Setup Before HIORD-
HCE(1, 2)- Hold Following HIORD-
HREG- Setup Before HIORD-
HREG- Hold Following HIORD-
HWAIT- Delay Falling from HIORD-
HWAIT- Width Time
HIOWR- High from HWAIT- High
RADIO TX DATA - TX PATH
t_SUIOWR
30
t_HIOWR
20
t_WIOWR
165
t_SUA
70
t_HA
20
t_SUCE
5
t_HCE
20
t_SUREG
5
t_HREG
0
t_DFWT
-
t_WWT
-
t_DRIOWR
0
-
92
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
35
ns
-
12,000
ns
-
-
ns
TXC Period
TXC Width Hi
TXC Width Lo
RADIO RX DATA - RX PATH
t_TXC
4* t_TMCK
-
t_CHM
31
-
t_CLM
31
-
-
ns
-
ns
-
ns
RX_RDY Setup Time to RXC Positive Edge (See Note 5)
RX_RDY Hold Time from RXC Positive Edge (See Note 6)
RX_PE2 Delay from RX_RDY deAssert (See Note 10)
RX_PE2 Low Pulse Width (See Note 9)
RXD Setup Time to RXC Positive Edge (See Note 7)
RXD Hold Time from RXC Positive Edge (See Note 7)
RXC Period (See Note 12)
RXC Width Hi
RXC Width Lo
NOTES:
t_{SURX_RDY}
10
-
-
ns
t_{HRX_RDY}
45
-
-
ns
t_{DRX_PE2}
-
3 * t_MCLK
-
ns
t_{WRX_PE2}
-
4 * t_MCLK
-
ns
t_SURXD
10
-
-
ns
t_HRXD
0
-
-
ns
t_RXC
-
3 * t_MCLK
-
ns
t_RCHM
31
-
-
ns
t_RCLM
31
-
-
ns
5. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is
sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.
6. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held
active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY
(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP
header length field are received. Therefore, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal
be cleared when the last RXD bit is received the hold time w/r RXC must be honored.
7. RXC positive edge clocks a flop which stores the RXD for internal usage.
8. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low.
9. RX_PE inactive width at BBP is 3 BBP CLK's. Since BBP CLK and MAC CLK can be async minimum should be 4 MAC CLKs.
10. When RX_RDY drops before expected number of RXD bits is received, then TX/RX FSM in mpctl.v signals timers which clear rx_pe2_int.
7