HFA3842B Datasheet, PDF (25/26 Pages) Intersil Corporation – PCMCIA/USB Wireless LAN Medium Access Controller

HFA3842B
both USB+ and USB- inputs are low continuously for more
than 2.5 microseconds. This condition resets the USB core
and certain other hardware, but does not perform a complete
soft reset. Hardware and software reset leave the
HFA3842B in the same state except in the case of soft reset
from the PC Card Host Interface, in which case the COR and
HCR registers come into play.
The MD[15:8] pin values are sampled during HRESET or
SRESET. These pins have internal 50K pull-down resistors.
External pull-up resistors (typically 10kΩ) are used for bits
that should be read as high at reset.
Table 12 summarizes the effect per pin. Table 13 provides
the MD15 and MD14 bit values required by the HFA3842B to
allow usage of Serial EEPROM Devices.
BITS
15:14
13
NAME
NVtype[1:01]
SHI_ENABLE
I2
4wire
11
Strldle
10
Mem16
9
NVds
8
ROMds
7
ISA Mode
6
FCRinIO
5:0
Spare
TABLE 12. INITIALIZATION STRAPPING OPTIONS ON MBUS DATA PINS
DEFAULT
FUNCTION
0
Indicates type of serial NV memory to be read by initialization firmware in on-chip ROM.
0
Use a Serial Host Interface (PC Card or ISA). When = 1 use a Serial Host Interlace (USB), and disable
all PC Card functions except Attribute space, for access to the COR and HCR Registers (see Section
4.3) for firmware debugging support.
1
Use 4-wire interface to SRAM (CS-, OE-, WEH-, WEL-) as appropriate when using x8 SRAMs. When
0 = selects 5-wire interface for use with x16 SRAM (CS-, OE-, WE-, UBE-, LBE-).
0
Start Idle. If ROMds = 0, then the “hardware” ignores this bit, but it is examined by the lCSROM boot
code which will halt after loading the serial NV. If ROMds = 1, then setting this bit will cause the
processor to wait for download of data From the AuxPort.
0
RAM and NV space at startup is 516. When = 0 RAM and NV space at startup is x8. IF starting from
off-chip NV memory this setting must indicate the width of the startup Flash EPROM. During
initialization, firmware can set separate widths for RAM and NV space in the Memory Control Register.
0
Disable mapping of off-chip control store to NV, space hence map off-chip control store to RAM
space). When = 0 off-chip control store is mapped to NV memory. This bit is used only to set initial
values in the MOR and CSCR registers. It controls the setting of the NVRE and MAPxx bits therein.
1
Disable on-chip ICSROM (Internal Control Store ROM - bootstrap code). When = 0 enable on-chip
ICS-ROM.
0
Set host interface control signals and address decoding For PC Card. When = 1 set host interface
signals and address decoding is for ISA bus, with all registers in I/O space and Attribute space
disabled. To use ISA mode, PHlenable must be = I to enable a Parallel Host Interface.
0
Enable I/O space decoding for the physical FCRs. When = 1, the COR. CSR, and PRR registers (see
Section 4.3) are accessible at I/O space offsets 0 x 40, 0 x 42, and 0 x 44 respectively. When = 0 these
registers are only accessible in Attribute space. This bit is ignored when PHIenable = 0, and is
overridden (forced = 1) when ISA mode = 1. FCRinIO = 1 is useful For PC Card operation PHIenable
= 1 lSA mode = 0 to allow non OS software to access the COR/HCR in OS environments where the
system software does not permit application software to access Attribute space.^a
00
Not assigned.
TABLE 13. SERIAL EEPROM SELECTION
MD15
MD14
DEVICE TYPE
FUNCTION
0
0
AT45DB011
Large Serial Device used to transfer firmware to SRAM
0
1
24C08 (Note)
Small Serial Device which contains only CIS. MAC goes idle after loading CIS and waits for host.
1
X
None
Modes not supported in firmware at this time. Consult factory for additional device types added.
NOTE: The operating frequency of the serial port is 400kHz with a voltage of 3.3V.
References
For Intersil documents available on the internet, see web site
www.intersil.com/
[1] IEEE Std 802.11-1999 Wireless LAN Medium Access
Control (MAC) and Physical Layer (PHY) Specification.
[2] HFA3860B Data Sheet, Direct Sequence Spread
Spectrum Baseband Processor, Intersil Corporation,
FN4594.
[3] HFA3861 Data Sheet, Direct Sequence Spread
Spectrum Baseband Processor, Intersil Corporation,
FN4699.
[4] HFA3783 Data Sheet, Quad IF, Intersil Corporation,
FN4633.
[5] HFA3683 Data Sheet, Direct Sequence Spread
Spectrum Baseband Processor, Intersil Corporation,
FN4634.
[6] PC Card Standard 1996, PCMCIA/JEIDA.
[7] AN9844 Application Note, Intersil Corporation,
“HFA3841 to PRISM II Connections”, AN9844.
[8] AN9926 Application Note, Intersil Corporation,
“HFA3842 and HFA3841 Differences”, AN9926.
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