HFA3842B Datasheet, PDF (18/26 Pages) Intersil Corporation – PCMCIA/USB Wireless LAN Medium Access Controller

HFA3842B
PHY BASEBAND PROCESSOR
The PHY baseband processor is programmed by HFA3842B
firmware.
The PRISM II baseband processor mode works as follows:
The Control Port consists of 3 signals: SD (serial data),
SCLK (serial clock), and CS_BAR (active-low chip select).
Control Port signaling for read and write operations is
illustrated in Figures 17 and 18 respectively. Detailed timing
relationships appear in Figure 19 and timing specifications
are contained in Table 7.
The BBP always uses the rising edge when clocking data on
the Control Port. This means that when the BBP is receiving
data it uses the rising edge of clock to sample; when driving
data, transitions occur on the rising edge.
Address bits 6 through 1 are significant for selecting
configuration registers. Address bits 7 and 0 are unused.
See the BBP Programming section for register addresses
and suggested values.
For read operations, the rising edge of R/W must occur after
the 7th but prior to the 8th rising edge of SCLK. This ensures
that the first data bit is clocked out of the BBP prior to the
edge used to clock it into the MAC.
For more detailed information on the Control Port and BBP
register programming see the HFA386x data sheets.
FID
BUFFER DESCRIPTOR
ACCESS (FIRMWARE)
ALLOCATE/
DEALLOCATE
REQUEST
OFFSET CENTER
BLOCK
A
OFFSET
VIRTUAL
FRAME BUFFER
STATUS
HEADER
BUFFER
MEMORY
HOST
BUS
DATA PORT
PRE-READ/
POST-WRITE
D
DATA
SCLK
SD
R/W
CS
SCLK
SD
R/W
CS
FIGURE 16. BLOCK DIAGRAM OF A BUFFER ACCESS PATH
FIRST ADDRESS BIT
FIRST DATABIT OUT
76 5 4 3 2 1 0 7 65 4 3 21 0
76 5 4 32 1
MSB
ADDRESS IN
07 7 6 6 5 4 3 2
MSB
DATA OUT
10
LSB
FIGURE 17. PRISM II BASEBAND PROCESSOR CONTROL PORT READ TIMING
76 5 4 32 1 07 6 54 3 2 10
76 5 4 3 21 0 76 5 4 3 21 0
MSB
ADDRESS IN
MSB
DATA IN
LSB
FIGURE 18. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING
18