HFA3842B Datasheet, PDF (23/26 Pages) Intersil Corporation – PCMCIA/USB Wireless LAN Medium Access Controller

HFA3842B
The USB along with USB support firmware provides an
alternate host interface for attaching an 802.11{b} WLAN
adapter to a host computer. This interface does not provide
“wireless USB” where USB packets are sent on the wireless
medium due to timing constraints in the USB protocol.
USB+ and USB- are the differential pair signals provided for
the user. These signals are capable of directly driving a USB
cable.
USB_DETECT is a 5V tolerant input to the HFA3842B device.
It is used to signal the MAC processor that a USB cable is
attached to the unit.
Complete details on the USB firmware for controlling this port
can be obtained by contacting the factory directly.
Power Sequencing
The HFA3842B provides a number of firmware controlled
port pins that are used for controlling the power sequencing
and other functions in the front end components of the PHY.
Packet transmission requires precise control of the radio.
Ideally, energy at the antenna ceases after the last symbol of
information has been transmitted. Additionally, the
transmit/receive switch must be controlled properly to protect
the receiver. It's also important to apply appropriate
modulation to the PA while it's active.
Signaling sequences for the beginning and end of normal
transmissions are illustrated in Figure 25. Table 10 lists
applicable delays.
A transmission begins with PE2 as shown in Figure 25. Next,
the transmit/receive switch is configured for transmission via
the differential pair TR_SW and TR_SW_BAR. This is
followed by TX_PE which activates the transmit state machine
in the BBP. Lastly, PA_PE activates the PA. Delays for these
signals related to the initiation of transmission are referenced
to PE2.
PE1
PE2
Immediately after the final data bit has been clocked out of the
HFA3842B, TX_PE is de-asserted. The HFA3842B then waits
for TXRDY to go inactive, signaling that the BBP has
modulated the final information-rich symbol. It then
immediately de-asserts PA_PE followed by placing the
transmit/receive switch in the receive position and ending with
PE2 going high. Delays for these signals related to the
termination of transmission are referenced to the rising edge
of PE2.
TABLE 10. TRANSMIT CONTROL TIMING SPECIFICATIONS
PARAMETER
PE2 to TR Switch
PE2 to PA_PE
PA_PE to PE2
TR Switch to PE2
SYMBOL
t_D1
t_D3
t_D4
t_D5
DELAY
2
3
3
2
TOLERANCE
±0.1
±0.1
±0.1
±0.1
UNITS
µs
µs
µs
µs
PE1 and PE2 encoding details are found in Table 11.
TABLE 11. POWER ENABLE STATES
PE1
PE2
PLL_PE
Power Down State
0
0
1
Receive State
1
1
1
Transmit State
1
0
1
PLL Active State
0
1
1
PLL Disable State
X
X
0
NOTE:
21. PLL_PE is controlled via the serial interface, and can be used to
disable the internal synthesizer, the actual synthesizer control is
an AND function of PLL_PE, and a result of the OR function of
PE1 and PE2. PE1 and PE2 will directly control the power
enable functionality of the LO buffer(s)/phase shifter.
Note that during normal receive and transmit operation that
PE1 is static and PE2 toggles for receive and transmit
states.
TR_SW
TR_SW_BAR
t_D1
t_D5
TX_PE
TX_RDY
PA_PE
t_D3
t_D4
FIGURE 25. TRANSMIT CONTROL SIGNAL SEQUENCING
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