HFA3842B Datasheet, PDF (24/26 Pages) Intersil Corporation – PCMCIA/USB Wireless LAN Medium Access Controller

HFA3842B
Master Clock
Prescaler
The HFA3842B contains a clock prescaler to provide
flexibility in the choice of clock input frequencies. For 11Mb/s
operation, the internal master clock, MCLK, must be
between 11MHz and 16MHz. The clock generator itself
requires an input from the prescaler that is twice the desired
MCLK frequency. Thus the lowest oscillator frequency that
can be used for an 11MHz MCLK is 22MHz. The prescaler
can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5).
Another way to look at it is that the divisor ratio between the
external clock source and the internal MCLK may be
integers between 2 and 14.
Typically, the 44MHz baseband clock is used as the input,
and the prescaler is set to divide by 2. Another useful
configuration is to set the prescaler to divide by 1.5 (resulting
in 44MHz ÷3) for an MCLK of 14.67MHz. Contact the factory
for further details on setting the clock prescaler register in
the HFA3842B.
Low-Frequency Crystal
The HFA3841 has an on-chip high-frequency oscillator that
can be used to generate the internal master clock (MCLK).
However, this on-chip high-frequency oscillator is almost
never used because the MAC controller can accept the
same clock signal as the PHY baseband processor (typically
44MHz), thereby avoiding the need for a separate, MAC-
specific oscillator in close proximity to the PHY RF circuitry.
Therefore, on the HFA3842B the high-frequency oscillator is
replaced by a low-frequency oscillator. This low-frequency
oscillator is intended for use with a 32.768KHz, tuning-fork
type watch crystal to permit accurate timekeeping with very
low power consumption during sleep state.
For the HFA3842B to achieve footprint compatibility with the
HFA3841, pin 40 (OSCIN on the HFA3841) becomes CLKIN,
which is the same function, when an external clock is
provided to the MAC controller (as is recommended when
using the HFA3842B with PRISM radios). The low-frequency
crystal attaches between pin 39 (which is a 3.3V power input
for the high-frequency oscillator on the HFA3841) and pin 41
(which is XTALO on the HFA3841, hence, unconnected if the
on-chip oscillator is not being used). Refer to Figure 26 for
additional details.
If a 32.768KHz crystal is connected, the resulting LF clock is
supplied to an interval timer to permit measuring sleep
intervals as well as providing a programmable wake-up time.
In addition, the CHOICE-W clock generator can operate
either from CLKIN or (very slowly) from the LF clock. Glitch-
free switching between these two clock sources, under
firmware control, is provided by two, non-architectural Strobe
functions (“FAST” and “SLOW”). In addition, during
hardware reset, the clock generator source is set to the LF
clock if no edges are detected on CLKIN for two cycles of the
LF clock (roughly 61 microseconds). This allows proper
initialization with omission of either clock source, since
without the LF crystal attached there will not be cycles of the
LF clock to activate the detection circuit. The ability to
initialize the HFA3842B using the LF oscillator to generate
MCLK allows the high-frequency (PHY) oscillator to be
powered down during sleep state, which is not possible with
the HFA3841. If this is done, firmware can turn on power to
the PHY oscillator upon wakeup, and use the interval timer
to measure the startup and stabilization period before
switching to use CLKIN.
Clock Generator
The HFA3842B can operate with MCLK frequencies up to at
least 25MHz and CLKIN frequencies of at least 50MHz. The
MCLK prescaler generates MCLK (and QCLK) from the
external clock provided at the CLKIN input, or from the
output of the LF oscillator. The MCLK prescaler divides the
selected input clock by any integer value between 2 and 16,
inclusive.
• When using a 44MHz CLKIN, as is typical for 802.11 or
802.11b controllers with a PC Card Host Interface, common
divisors are 3 (14.67MHz), 4 (11MHz), or 5 (8.8MHz)
• When using a 48MHz CLKIN, as is typical for 802.11 or
802.11b controllers with a USB host interface, common
divisors are 3 (16MHz), 4 (12MHz), or 6 (8MHz)
• It is anticipated that a controller for the 802.11a,
mandatory data rates will need to operate at an MCLK
frequency of a least 24MHz, hence a CLKIN frequency of
at least 48MHz.
The MCLK prescaler is set to divide by 16 at hardware reset
to allow initialization firmware to be executed from slow
memory devices at any CLKIN frequency. The MCLK
prescaler generates glitch free output when the divisor is
changed. This allows firmware to change the MCLK
frequency during operation, which is especially useful to
selectively reduce operating speed, thereby conserving
power, when full speed processing is not required.
39
LF XTALI
X1
41
LFXTALO
22pF
C1
10MΩ
C2
4700pF
FIGURE 26. 32.768kHz CRYSTAL
Power On Reset Configuration
The HFA3842B supports both hardware and software reset
functions. Hardware reset is caused by assertion of the
RESET input. When using the PC Card host interface,
software reset is caused by setting the Sreset bit in the
Configuration Option Register (COR[71]. When using the
USB host interface, the soft reset function is invoked when
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