ISL5216_05 Datasheet, PDF (63/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
Feature Changes
1. Core voltage lowered from 3.3V to 2.5V for lower power
operation (I/O supply voltage remains at 3.3V). Maximum
speed increased from 70MHz to 80MHz.
2. Added JTAG boundary scan test pins.
3. Added readback capability to all the control registers.
See Table of Indirect Read Address Registers for
complete listing. Also added filter compute engine data
RAM read / write test mode via microprocessor interface
(F800H bit 15).
4. Added SYNCI0, SYNCI1, SYNCI2 and SYNCI3 pins to
serve as SYNCI for individual channels. These inputs are
OR’d together with the original (HSP50216) SYNCI so
that SYNCI still functions as a global input.
5. Added GWA register F80AH to generate a SYNCO as in
F809H, but which is also internally fed back to SYNCI.
6. Added more CIC barrel shifter range. Maximum shift
range was increased by 16 from 31 (HSP50216) to 47,
allowing for unit gain at lower CIC decimations and CIC
bypassing (see CIC Filter section for restrictions). This
added bit 19 to IWA *004H.
7. Added additional input pins for 14/3, 15/2 and 16/1
floating point input modes. Also added an additional 6dB
to the old 14/2 mode. This added bits 20:16 to IWA *000H
and 20:16 to GWA F804H (input level detector).
8. Added a complex input mode. In this mode, complex (I
and Q) data can be multiplexed with the I input first and Q
input second. The ENIx signal indicates the clock cycle
when I is valid, and the Q data is taken on either the next
input clock or the one two clocks after I. This added bits
24:22 to IWA *000H and 24:22 to GWA F804H. Complex
input mode is not valid for the input level detector (only I
samples are processed).
9. Added a programmable delay to the sin / cos path to
correct for misalignment between the input data enables
and the NCO enables when input samples are unevenly
spaced in the gated input mode. This added bit 21 to IWA
*000H. If set, the misalignment is corrected. Can be set
to 0 to retain HSP50216 behavior.
10. Increased carrier phase offset resolution from 3 to 16 bits.
The original 3 bits (*004H bits 8:6) are added to a 16 bit
value loaded into new IWA register *01CH. Register
*01CH is zeroed by the reset pin.
11. Changed microprocessor FIFO read decoding to remove
the CE to RD timing constraint (µPmode = 0). For
µPmode = 1 the constraint was from ADDx, CE and R/W
set up to the falling edge of DSTRB.
12. Changed serial output control logic to allow as few as five
clocks between output samples rather than the minimum
of seven clocks between inputs to the serial output
section required by the HSP50216.
13. Fixed the delay mode issue in the serial output control
logic (in the HSP50216, if delayed samples extended to
within seven samples of the new input to the serial output
section the last sample could be dropped).
14. Fixed a problem in the timing NCO circuit that, under
certain circumstances, could cause lost samples or no
output.
15. Added BIST (built-in self test).
16. Added a reset of the CIC’s comb data registers on a front
end reset. This reduces the transient due to old data in
the comb when the decimation counters restart.
17. Changed filter routing path 3. In HSP50216 path 3 routed
intermediate filter calculations both to the filter compute
engine input and directly to I2 and Q2 outputs. In the
ISL5216, path 3 routes data from the filter compute
engine output through the FIFO and AGC to I2 and Q2.
See Back End Data Routing figure.
18. Changed the mask revision field in the status register to
3. The HSP50216 rev. C reported a value of 2.
19. Changed Timing and Carrier NCO frequency readback
register locations. On the HSP50216, Carrier NCO
frequency readback was at IRA *006H. This has changed
to *005H on the ISL5216. Likewise Timing NCO
frequency readback has changed from IRA *009H (for the
upper 32 bits) on the HSP50216 to *007H for the upper
32 bits and *008H for the lower 24 bits. See Table of
Indirect Read Address Registers for complete listing of
readback registers.
20. Removed bits 20:17 from GWA register F800H (test
control register). Bit 0 no longer needs to be set to route
bits 31:21 to their corresponding output pins (see bit 16
description).
All new control bits are inactive if set to zero for backward
compatibility with HSP50216 software.
Power-up Sequencing
The ISL5216 core and I/O blocks are isolated by structures
which may become forward biased if the supply voltages are
not at specified levels. During the power-up and power-down
operations, differences in the starting point and ramp rates of
the two supplies may cause current to flow in the isolation
structures which, when prolonged and excessive, can
reduce the usable life of the device.
In general, the most preferred case would be to power-up
the core and I/O structures simultaneously. However, it is
also safe to power-up the core prior to the I/O block if
simultaneous application of the supplies is not possible. In
this case, the I/O voltage should be applied in 10ms to
100ms nominally to preserve supply component reliability.
Bringing the core and I/O supplies to their respective
regulation levels in a maximum time frame of a 100ms,
moderates the stresses placed on both, the power supply
and the ISL5216.
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July 8, 2005