ISL5216_05 Datasheet, PDF (19/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
Instruction Bit Fields
BIT
POSITIONS
8:0
FUNCTION
Instruction
14:9
FIR Type
17:15
Steps per FIR
INSTRUCTION BIT FIELDS
DESCRIPTION
Instruction Field Bit Mapping
Bit
8
7
6
5
4
3
2
1
0
Type
WAIT 0
0
X
X
X
X
C
C
C
FIR 0
1
Start IncrRS DecrSel DecrEn LdLp DecrLp EnU/C
JUMP 1
J
J
J
J
J
C
C
C
(NOPs and loading the loop counter are special cases of the FIR instruction).
XXXX = ignored.
JJJJJ = jump destination (sequence step number).
CCC = condition code.
000 = ! (waitcount ≥ threshold) -- See IWA = *00Ch, bits 9:0 for threshold details.
001 = waitcount ≥ threshold -- See IWA = *00Ch, bits 9:0 for threshold details.
010 = loop counter ≠ 0.
011 = loop counter = 0.
100 = ! (RSCO) (RSCO - resampler NCO carry output).
101 = RSCO.
110 = sync (if enabled) or µP controlled bit.
111 = always.
Start = load parameters and start filter computation, set to zero for no-ops, loop counter loads.
IncrRS = increment resampler during this filter.
Increments on start or at each FIR output depending on µPcontrol bit.
DecrSel = selects between two decrement values for the wait counter.
DecrEn = decrement wait count on starting this instruction.
LdLp
= load loop counter with the data in the I(20:9) bit field.
The start bit should not be set when this bit is set.
DecrLp = decrement loop counter on starting this instruction.
EnU/C
= enable U/C counter with this FIR.
This multiplies the data by 1, j, -1, -j.
The multiplication factor changes each time the filter runs.
FIR Parameter Bit Fields
14:9
FIR type.
000000 NOP.
000001 Decimating FIR, Even Symmetric, Even # Taps.
000010 Decimating FIR, Even Symmetric, Odd # Taps.
000011 Decimating FIR, Odd Symmetric, Even # Taps.
000100 Decimating FIR, Odd Symmetric, Odd # Taps.
000101 Decimating FIR, Asymmetric.
001000 Resampling FIR, Asymmetric.
001001 Interpolating HBF.
100000 Decimating FIR, Complex (Asymmetric).
NOTES:
14. Regular interpolation FIRs are successive runs of a FIR with no data address increment, but with
coefficient start address increments.
15. Decimating HBFs are even symmetric, odd number of taps but with different data step sizes.
16. U/C FIR is a normal FIR with the U/C bit enabled.
17. Other codes may be added in the future.
Specifies the number of steps per FIR instruction sequence (load with value minus 1)
(set to 0 for all FIR types except complex which is set to 1).
19
July 8, 2005