ISL5216_05 Datasheet, PDF (23/65 Pages) Intersil Corporation – Four-Channel Programmable Digital DownConverter

ISL5216
Wait Preload Register
This register (IWA register *00Ch) holds the wait counter
threshold and two wait counter decrement values. Each is
ten bits. The wait counter counts filter input samples until the
count is greater than or equal to the threshold. The wait
counter then asserts a flag to the filter compute engine.
The wait counter threshold is typically set to the total number
of input samples needed to generate a filter output. A “WAIT”
instruction in the filter compute engine waits for the wait
counter flag signal before proceeding. The filter compute
engine would then compute all the filters needed to produce
an output and then would jump back to the “WAIT”
instruction.
The wait counter is implemented with an accumulator. This
allows the count to go beyond the threshold without losing
the sample count. Two bits in the FIR instruction decrement
the wait counter (subtract a value) and select the decrement
value. The decrement value is typically the number of
samples needed for an output (total decimation), though it
can be a different value to ignore inputs and shift the timing.
(The read pointer increment must be adjusted as well.)
The filter compute engine sequencer does not count each
input sample or track whether each filter is ready to run.
Instead, the wait counter is used to determine whether there
are enough input samples to compute all the filters in the
chain and get an output sample from the entire filter chain.
This adds some additional delay since intermediate results
are not precalculated, but it simplifies the filter control. The
number of samples needed is equal to the total decimation
of the filter chain. For example, with two decimate-by-2
halfband filters and a decimate-by-2 shaping FIR, the total
decimation would be 8 so 8 samples are needed to compute
an output. HBF1 would compute four times to generate four
inputs to HBF2. HBF2 would compute twice to generate the
two samples that the shaping FIR needs to compute an
output.
Resampler
The resampler is an NCO controlled polyphase filter that allows
the output sample rate to have a non-integer relationship to the
input sample rate. The filter engine can be viewed conceptually
as a fixed interpolate-by-32 filter, followed by an NCO controlled
decimator. The Resampler NCO is similar to the carrier NCO
phase accumulator but does not include the SIN/COS section.
It provides the resampler output pulse and associated phase
information to logic that determines the nearest of the 32
available phase points for a given output sample.
The center frequency (output sample rate) control is double
buffered, i.e., the control word is written to one register via the
microprocessor interface and then transferred to another
(active) register on a write to the timing NCO center frequency
update strobe location (IWA register *009h) or on a SYNCI (if
enabled). As it is not possible to represent some frequencies
exactly with an NCO and therefore, phase error accumulates
eventually causing a bit slip, the phase accumulator length
has been sized to where the error is insignificant. At a
resampler input rate of 1MHz, half an LSB of error in loading
the 56-bit accumulator is 7*10^-12 degrees. After one year, the
accumulated phase error is only 0.2*10^-3 of a bit (< 1/10 of a
degree). The NCO update by the filter compute engine is
typically at the resampler's input rate, and is enabled by the
IncrRS bit in the filter instruction word. The NCO then rolls
over at a fraction of the resampler input rate. The output
sample rate is (f_IN/ 2⁵⁶)*N, where f_IN is the resampler input
rate and N is the phase accumulated per resampler input
sample (IWA registers *007h and *008h). N must be between
40000000000000h and FFFFFFFFFFFFFFh corresponding
to decimations from 4 to (1 + 2^-56), respectively. Generally,
however, a range of 80000000000000h to
FFFFFFFFFFFFFFh (providing decimation from 2 to (1 + 2^-56),
respectively) is sufficient for most applications since integer
decimation can be done more efficiently in the preceding CIC
and halfband filters. The resampler changes the sample rate
by computing an output at each input which causes the NCO
to roll over. If an output is to be computed, the nearest of the
32 available points from the polyphase structure is used.
Because outputs are generated only on input samples which
cause an NCO roll over, output samples will in general not be
evenly spaced. The FIFO/TIMER block between the filter
compute engine and the AGC is provided to improve output
sample spacing for presentation to the serial data output
formatter section (see IWA=*00Ah bits 11:0 description). If
D/A converted directly, there would be artifacts from the
uneven sample spacing, but if the samples are stored and
reconstructed at the proper rate (the NCO rollover rate), the
signal would have only the distortion produced by
interpolation image leakage and the time quantization (phase
jitter) due to the finite number of interpolation filter phases.
The polyphase filter has 192 coefficients implemented as 32
phases, each of which having 6 taps (6 x 32 = 192). These
coefficients are provided in Table 54. The stopband
attenuation of the filter is greater than 60dB, as shown in
Figures 18–20. The signal to total image power ratio is
approximately 55dB, due to the aliasing of the interpolation
images. If the output is at least 2x the baud rate, the 32
interpolation phases yield an effective sample rate of 64x the
baud rate or approximately 1.5% (1/64 resampler input
sample period) maximum timing error.
AGC
The AGC Section provides gain to small signals, after the
large signals and out-of-band noise have been filtered out, to
ensure that small signals have sufficient bit resolution in the
output formatter. The AGC can also be used to manually set
the gain. The AGC optimizes the bit resolution for a variety of
input amplitude signal levels. The AGC loop automatically
adds gain to bring small signals from the lower bits of the
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July 8, 2005