ISL78236 Datasheet, PDF (6/24 Pages) Intersil Corporation – Dual 3A Current Sharing 2.5MHz High Efficiency Synchronous Buck Regulator

Pin Configuration
ISL78236
ISL78236
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
LX2 1
18 LX1
VIN2 2
17 VIN1
VIN2 3
EN2 ₄
25
PAD
16 ^VIN1
15 VDD
PG2 5
14 SS
FB2 6
13 EN1
7 8 9 10 11 12
Pin Descriptions
PIN
NUMBER
1, 24
4
5
6
7
8
9
10
11
12
13
SYMBOL
LX2
EN2
PG2
FB2
COMP
NC
FB1
SGND
PG1
SYNC
EN1
DESCRIPTION
Switching node connection for Channel 2.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown VOUT2 and discharge output
capacitor when driven to low. Do not leave this pin floating.
Active high Power-Good (PG) indicator for Channel 2. After power-up or EN2 High, this output is a 1ms delayed
Power-Good signal for the Channel 2 output voltage.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier.
The output voltage is set by an external resistor divider from VOUT2 connected to FB2. The power-good output and
undervoltage lockout protection circuitry uses FB2 to monitor the Channel 1 regulator output voltage.
COMP pin is treated as a No Connect in dual output mode operation, using only the internal compensation. If the SS pin
is tied to a soft-start capacitor, external compensation is automatically used. An additional external network across
COMP and SGND is required to improve the loop compensation of the amplifier in parallel current sharing operation.
Connect an external RC network on COMP pin for parallel mode operation.
No connect pin; please tie to GND for thermal relief.
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier.
The output voltage is set by an external resistor divider from VOUT1 connected to FB1. The power-good output and
undervoltage lockout protection circuitry uses FB1 to monitor the Channel 1 regulator output voltage.
System ground.
Active high Power-Good (PG) indicator for Channel 1. After power-up or EN1 High, this output is a 1ms delayed
power-good signal for the Channel 1 output voltage.
Connect to logic high or input voltage VIN. Connect to an external function generator for external synchronization.
Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shut down VOUT1 and discharge
output capacitor when driven to low. Do not leave this pin floating.
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FN8624.0
April 28, 2014