ISL78236 Datasheet, PDF (18/24 Pages) Intersil Corporation – Dual 3A Current Sharing 2.5MHz High Efficiency Synchronous Buck Regulator

ISL78236
Theory of Operation
The ISL78236 is a dual 3A or single current sharing 6A step-down
switching regulator optimized for low output ripple point-of-load
power in automotive applications. The regulator operates at
2.5MHz internally fixed switching frequency allowing small output
filter components while maintaining up to 95% efficiency. The two
channels are 180° out-of-phase operation to reduce input ripple
currents and EMI. The supply current is typically only 8µA when the
regulator is shutdown.
PWM Control Scheme
Pulling the SYNC pin HI (>1.5V) forces the converter into PWM mode
in the next switching cycle regardless of output current. Each of the
channels of the ISL78236 employ the current-mode pulse-width
modulation (PWM) control scheme for fast transient response and
pulse-by-pulse current limiting, as shown in the “Block Diagram” on
page 5 with waveforms in Figure 49. The current loop consists of
the oscillator, the PWM COMP comparator, current sensing circuit,
and the slope compensation for the current loop stability. The
current sensing circuit consists of the resistance of the P-channel
MOSFET when it is turned on and the current sense amplifier CSA.
The gain for the current sensing circuit is typically 0.2V/A. The
control reference for the current loops comes from the error
amplifier, EAMP, of the voltage loop.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA1 (or CSA2 on Channel 2) and the
compensation slope (0.46V/µs) reaches the control reference of
the current loop, the PWM COMP comparator sends a signal to the
PWM logic to turn off the P-MOSFET and to turn on the N-channel
MOSFET. The N-MOSFET stays on until the end of the PWM cycle.
Figure 49 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA_ output.
V_EAMP
V_CSA1
Duty
Cycle
I_L
V_OUT
FIGURE 49. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.8V
reference voltage to the voltage control loop. The feedback
voltage signal comes from the FB pin. The soft-start block only
affects the operation during the start-up and will be discussed
separately. The error amplifier is a transconductance amplifier
that converts the voltage error signal to a current output. The
voltage loop is internally compensated with the 27pF and 390kΩ
RC network. The maximum EAMP voltage output is precisely
clamped to the bandgap voltage (1.172V).
Synchronization Control
The synchronization frequency can be operated to a range of
6MHz to 8MHz by an external signal applied to the SYNC pin. The
SYNC pin has logic threshold levels of 0.4V and 1.5V for LOW and
HIGH respectively, to allow for external clock signals to be of
different magnitude regardless of supply voltage to ISL78236.
The 1st falling edge on the SYNC triggers the rising edge of the
PWM ON pulse of Channel 1. The 2nd falling edge of the SYNC
triggers the rising edge of the PWM ON pulse of Channel 2.
Typically, the pulse width of the SYNC signal should be 50% duty
cycle, however, it is recommended that the pulse width be in the
range of 50ns to 100ns for valid synchronization. This process
alternates indefinitely allowing 180°output phase operation
between the two channels. It is important to note that this
operation makes the switching frequency of each channel 1/2 of
the SYNC frequency. Thus, Channel 1 and Channel 2 have a
synchronized switching frequency of 3MHz to 4MHz.
Output Current Sharing
The ISL78236 dual outputs are paralleled for multi-phase
operation in order to support 6A output. Channel 1 and Channel 2
switches 180° out-of-phase to reduce input ripple currents. In
parallel configuration, external soft-start should be used to ensure
proper full loading start-up. Connect the FBx pins together and
connect a soft-start capacitor from SS pin to GND. External
compensation using the COMP pin is required for current sharing
operation. Please see Table 2 for recommended values in current
sharing mode. The current sharing balancing is dependent on the
current sense amplifier matching between the two channels. The
matching is internally trimmed and provides excellent balancing
of output currents. See Figures 47 and 48 for typical output
current matching.
Overcurrent Protection
CSA1 and CSA2 are used to monitor Output 1 and Output 2
channels respectively. The overcurrent protection is realized by
monitoring the CSA output with the OCP threshold logic, as
shown in the “Block Diagram” on page 5. The current sensing
circuit has a gain of 0.2V/A, from the P-MOSFET current to the
CSA output. When the CSA output reaches the threshold, the
OCP comparator is tripped to turn off the P-MOSFET immediately.
The overcurrent function protects the switching converter from a
shorted output by monitoring the current flowing through the
upper MOSFETs.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the Overcurrent Fault Counter is set to 1 and the
Overcurrent Condition Flag is set from LOW to HIGH. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC Fault Counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shut down under an
Overcurrent Fault Condition. An Overcurrent Fault Condition will
result with the regulator attempting to restart in a hiccup mode
with the delay between restarts being 8 soft-start periods. At the
Submit Document Feedback ₁₈
FN8624.0
April 28, 2014