ISL78236 Datasheet, PDF (21/24 Pages) Intersil Corporation – Dual 3A Current Sharing 2.5MHz High Efficiency Synchronous Buck Regulator

ISL78236
^iin
V^in
+
^iL L_P
ILd^ 1:D ^{Vind^}
R_LP
RT
vo^
Rc
Ro
Co
d^
Ti(S)
K
Fm
+
He(S)
Tv(S)
v^comp _-Av(S)
FIGURE 50. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
V_o
R₂
C₃
V_FB
-
V_COMP
R₃
V_REF
GM
+
R₆
C₇
C₆
FIGURE 51. TYPE II COMPENSATOR
Figure 51 shows the type II compensator and its transfer function
is expressed, as shown in Equation 7:
A_vS=
-^vˆ---C-_v-ˆ--^O-_F---_BM-----^P-- =
------------------^G-----^M-------^---^R----³-------------------
C₆ + C₇  R₂ + R₃
---^---¹-----+------^--------^cS------^z------¹----^---^---¹-----+------^--------^c-^S-----z------²----^----
S
 ¹
+
^-----_c^S---_p^---₁^{- }


1
+
^-----_c^S---_p^---₂^{- }
(EQ. 7)
where,
_cz1
=
-------¹-------
R₆C₆
,
_cz2 =
-_R----₂--¹-_C-----₃- _cp1=
R^--C---₆^-6--C^---+--₆^--C-C^----7-₇^{- cp2=}
--^R----²-----+----^R-----³--
C₃R₂R₃
Compensator design goal:
High DC gain
Choose Loop bandwidth f_c 100kHz or below
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of f_c has a unity gain.
Therefore, the compensator resistance R₆ is determined by
Equation 8.
R₆ = -²---^-_G---^f--_M^c---^V---_-^o--_V--^C--_F--^o--_B--^R----^t = 15.710³  f_cV_oC_o
(EQ. 8)
Where R_t is the current sense amplifier gain (0.2V/A) and GM is
the trans-conductance, g_m, of the voltage error amplifier in each
phase (see “Electrical Specification” Table for “Error Amplifier
Trans-Conductance” on page 8). Compensator capacitor C₆ and
C₇ is then given by Equation 9.
C₆
=
R_-----o---C_-----o-
R₆
=
-^V----^o---^C-----^o-
I_oR₆
,C₇ =
max of
(-^R---_R-^c---^C-₆----^o-,-_---_f--_s-¹--_R-----₆-)
(EQ. 9)
An optional zero can boost the phase margin. _CZ2 is a zero due
to R₂ and C₃
C₃=
-------¹--------
f_cR₂
(EQ. 10)
Example: V_IN = 5V, V_O = 1.8V, I_O = 3A, Fs = 2.5MHz, R₂ = 124k,
R₃ = 100k, C_o = 2X22µF/3mΩ, L = 0.6µH, f_c = 100kHz, then
compensator resistance R₆:
R₆ = 15.710³  100kHz  1.8V  44F = 124k
(EQ. 11)
Use a standard 124kΩ 1% tolerance or better resistor.
C₆
=
1_----._--8_---V_------_---4_---4_----_----F_--
3A  124k
=
213 p F
(EQ. 12)
C₇=
m a x (-³---^m------^------^---⁴---⁴----^----^F-- ,-------------------------¹---------------------------) =
124k   2.5MHz  124k
(1 p F,1 p F)
(EQ. 13)
Use the closest standard values for C₆ and C₇. There is
approximately 2pF parasitic capacitance from V_COMP to GND;
Therefore, C₇ is optional. Use C₆ = 220pF and C₇ = OPEN.
C₃=
-------------------------¹---------------------------
  100kHz  124k
=
26 p F
(EQ. 14)
Use C₃ = 22pF. Note that C₃ may increase the loop bandwidth
from previous estimated value.
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL78236, the power
loop is composed of the output inductor L’s, the output capacitor
C_OUT1 and C_OUT2, the LX’s pins, and the PGND pin. It is necessary to
make the power loop as small as possible and the connecting traces
among them should be direct, short and wide. The switching node of
the converter, the LX pins, and the traces connected to the node are
very noisy, so keep the voltage feedback trace away from these
noisy traces. The FB network should be as close as possible to its FB
pin. SGND should have one single connection to PGND. The input
capacitor should be placed as closely as possible to the VIN pin.
Also, the ground of the input and output capacitors should be
connected as closely as possible. The heat of the IC is mainly
dissipated through the thermal pad. Maximizing the copper area
connected to the thermal pad is preferable. In addition, a solid
ground plane is helpful for better EMI performance. It is
recommended to add at least 5 vias ground connection within the
pad for the best thermal relief.
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FN8624.0
April 28, 2014