ISL12023 Datasheet, PDF (6/28 Pages) Intersil Corporation – Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

ISL12023
SDA vs SCL Timing
t_F
t_HIGH
t_LOW
t_R
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t_SU:DAT
t_HD:STA
t_HD:DAT
t_AA
t_DH
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V_DD = 5V
5.0V
SDA,
IRQ AND FOUT
1533Ω
FOR V_OL= 0.4V
AND I_OL = 3mA
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V_DD = 5.0V
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A
Center Line is
High Impedance
t_SU:STO
t_BUF
6
FN6682.2
June 24, 2009