ISL12023 Datasheet, PDF (22/28 Pages) Intersil Corporation – Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

ISL12023
TABLE 24. XT0 VALUES
XT<4:0>
TURNOVER TEMPERATURE
01111
32.5
01110
32.0
01101
31.5
01100
31
01011
30.5
01010
30
01001
29.5
01000
29.0
00111
28.5
00110
28.0
00101
27.5
00100
27.0
00011
26.5
00010
26.0
00001
25.5
00000
25.0
10000
25.0
10001
24.5
10010
24.0
10011
23.5
10100
23.0
10101
22.5
10110
22.0
10111
21.5
11000
21.0
11001
20.5
11010
20.0
11011
19.5
11100
19.0
11101
18.5
11110
18.0
11111
17.5
ALPHA Hot Register (ALPHAH)
TABLE 25. ALPHAH REGISTER
ADDR 7
6
5
4
3
2
1
0
2Dh D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0
The ALPHA Hot variable is 7 bits and is defined as the
temperature coefficient of Crystal from the XT0 value to
+85°C (both Alpha Hot and Alpha Cold must be programmed
to provide full temperature compensation). It is normally
given in units of ppm/°C², with a typical value of -0.034. Like
the ALPHA Cold version, a scaled version of the absolute
value of this coefficient is used in order to get an integer
value. Therefore, ALP_H<7:0> is defined as the (|Actual
Alpha Hot Value| x 2048) and converted to binary. For
example, a crystal with Alpha Hot of -0.034ppm/°C² is first
scaled (|2048*(-0.034)| = 70d) and then converted to a
binary number of 01000110b.
The practical range of Actual ALPHAH values is from
-0.020 to -0.060.
The ISL12023 has a preset ALPHAH value corresponding to
the crystal in the module. This value is recalled on initial
power-up and should never be changed for best temperature
compensation performance, although the user may override
this preset value if so desired.
The ALPHAH register should only be changed while the TSE
(Temp Sense Enable) bit is “0”.
User Registers (Accessed by Using Slave
Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
The separate I²C slave address must be used to read and
write to these registers.
I²C Serial Interface
The ISL12023 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12023 operates as a slave device in all applications.
All communication over the I²C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 14). On
power-up of the ISL12023, the SDA pin is in the input mode.
All I²C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12023 continuously monitors the SDA
and SCL lines for the START condition and does not respond
to any command until this condition is met (see Figure 14). A
START condition is ignored during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 14). A STOP condition at the end
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FN6682.2
June 24, 2009