ISL12023 Datasheet, PDF (18/28 Pages) Intersil Corporation – Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

ISL12023
BETA values are limited in the range from 01000 to 11111 as
shown in Table 16. To use Table 16, the device is tested at
two AT settings as follows:
BETA VALUES = (AT(max) - AT(min))/63, where:
AT(max) = F_OUT in ppm (at AT = 00H) and
AT(min) = F_OUT in ppm (at AT = 3FH).
The BETA VALUES result is indexed in the right hand
column and the resulting Beta factor (for the register) is in
the same row in the left column.
The value for BETA should only be changed while the TSE
(Temp Sense Enable) bit is “0”. The procedure for writing the
BETA register involves two steps. First, write the new value
of BETA with TSE = 0. Then write the same value of BETA
with TSE = 1. This will insure the next temp sense cycle will
use the new BETA value.
TABLE 16. BETA VALUES
BETA<4:0>
AT STEP ADJUSTMENT
01000
0.5000
00111
0.5625
00110
0.6250
00101
0.6875
00100
0.7500
00011
0.8125
00010
0.8750
00001
0.9375
00000
1.0000
10000
1.0625
10001
1.1250
10010
1.1875
10011
1.2500
10100
1.3125
10101
1.3750
10110
1.4375
10111
1.5000
11000
1.5625
11001
1.6250
11010
1.6875
11011
1.7500
11100
1.8125
11101
1.8750
11110
1.9375
11111
2.0000
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only, the user cannot overwrite a value to
this register. This value is accessible as a means of monitoring
the temperature compensation function. See Table 17.
TABLE 17. FINAL ANALOG TRIMMING REGISTER
ADDR 7 6 5
4
3
2
1
0
0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
Final Digital Trimming Register (FDTR)
This register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. The value is accessible as a means of monitoring
the temperature compensation function. The corresponding
clock adjustment values are shown in Table 19. The DT
setting has both positive and negative settings to adjust for
any offset in the crystal.
.
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
ADDR 7 6 5
4
3
2
1
0
0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
DIGITAL TRIMMING REGISTER
FDTR<2:0>
DECIMAL
ADJUSTMENT
(ppm)
00000
0
0
00001
1
30.5
00010
2
61
00011
3
91.5
00100
4
122
00101
5
152.5
00110
6
183
00111
7
213.5
01000
8
244
01001
9
274.5
01010
10
305
10000
0
0
10001
-1
-30.5
10010
-2
-61
10011
-3
-91.5
10100
-4
-122
10101
-5
-152.5
10110
-6
-183
10111
-7
-213.5
11000
-8
-244
11001
-9
-274.5
11010
-10
-305
18
FN6682.2
June 24, 2009