ISL12023 Datasheet, PDF (4/28 Pages) Intersil Corporation – Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

ISL12023
Power-Down Timing Test Conditions: V_DD = +2.7 to +5.5V, T_A = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 9) (Note 5) (Note 9)
V_{DD SR-} V_DD Negative Slew Rate
10
UNITS
V/ms
NOTES
6
I²C Interface Specifications Test Conditions: V_DD = +2.7 to +5.5V, T_A = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 5) (Note 9)
UNITS
V_IL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x V_DD
V
V_IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V_DD
V_DD + 0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x V_DD
V
V_OL
SDA Output Buffer LOW Voltage, V_DD = 5V, I_OL = 3mA
Sinking 3mA
0
0.02
0.4
V
C_PIN
f_SCL
t_IN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
T_A = +25°C, f = 1MHz,
V_DD = 5V, V_IN = 0V,
V_OUT = 0V
Any pulse narrower than the
max spec is suppressed.
10
pF
400
kHz
50
ns
t_AA
t_BUF
SCL Falling Edge To SDA Output
Data Valid
Time the Bus must be Free Before
the Start of a New Transmission
SCL falling edge crossing 30%
of V_DD, until SDA exits the
30% to 70% of V_DD window.
SDA crossing 70% of V_DD
during a STOP condition, to
SDA crossing 70% of V_DD
during the following START
condition.
1300
900
ns
ns
t_LOW Clock LOW Time
Measured at the 30% of V_DD
1300
ns
crossing.
t_HIGH Clock HIGH Time
Measured at the 70% of V_DD
600
ns
crossing.
t_SU:STA START Condition Setup Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Setup Time
t_HD:DAT Input Data Hold Time
t_SU:STO STOP Condition Setup Time
SCL rising edge to SDA falling
600
edge. Both crossing 70% of
V_DD.
From SDA falling edge
600
crossing 30% of V_DD to SCL
falling edge crossing 70% of
V_DD.
From SDA exiting the 30% to
100
70% of V_DD window, to SCL
rising edge crossing 30% of
V_DD.
From SCL falling edge
0
crossing 30% of V_DD to SDA
entering the 30% to 70% of
V_DD window.
From SCL rising edge
600
crossing 70% of V_DD, to SDA
rising edge crossing 30% of
V_DD.
ns
ns
ns
900
ns
ns
NOTES
7, 8
7, 8
4
FN6682.2
June 24, 2009