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| ISL12022MIBZ-T7A Datasheet, PDF (6/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving | |||
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ISL12022M
DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
NOTES
OSCILLATOR ACCURACY
ÎFoutI
ÎFoutR
ÎFoutT
ÎFoutV
Temp
Oscillator Initial Accuracy
Oscillator Accuracy after Reflow Cycle
Oscillator Stability vs Temperature
Oscillator Stability vs Voltage
Temperature Sensor Accuracy
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL Output Low Voltage
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
2.7V ⤠VDD ⤠5.5V
VDD = VBAT = 3.3V
VDD = 5V, IOL = 3mA
VDD = 2.7V, IOL = 1mA
-2
+8
ppm 6, 17
±5
ppm 6, 17
±2
ppm 6, 18
-3
+3
ppm
19
±2
°C
13
0.4
V
0.4
V
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
VDDSR-
VDDSR+
VDD Negative Slew Rate
VDD Positive Slew Rate, minimum
0.05
10
V/ms
V/ms
NOTES
12
16
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 8)
MAX
(Note 7)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
13, 14
VOL
SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA
Sinking 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V, VOUT = 0V
fSCL
SCL Frequency
tIN
Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10
pF
13, 14
400
kHz
50
ns
tAA
SCL Falling Edge to SDA Output SCL falling edge crossing
Data Valid
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before SDA crossing 70% of VDD
1300
ns
the Start of a New Transmission during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
tLOW
Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing.
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing.
6
FN6668.9
June 20, 2012
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