ISL12022MIBZ-T7A Datasheet, PDF (20/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022M
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only; the user cannot overwrite a value to this
register. This value is accessible as a means of monitoring the
temperature compensation function. See Table 17 and Table 18 (for
values).
ADDR
0Eh
TABLE 17. FINAL ANALOG TRIMMING REGISTER
76
5
4
3
2
1
0
0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. The value is accessible as a means of monitoring
the temperature compensation function. The corresponding
clock adjustment values are shown in Table 19. The FDTR setting
has both positive and negative settings to adjust for any offset in
the crystal.
.
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
ADDR 7 6 5
4
3
2
1
0
0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL
TRIMMING REGISTER
FDTR<4:0>
DECIMAL
ppm ADJUSTMENT
00000
0
0
00001
1
30.5
00010
2
61
00011
3
91.5
00100
4
122
00101
5
152.5
00110
6
183
00111
7
213.5
01000
8
244
01001
9
274.5
01010
10
305
10000
0
0
10001
-1
-30.5
10010
-2
-61
10011
-3
-91.5
10100
-4
-122
10101
-5
-152.5
10110
-6
-183
10111
-7
-213.5
11000
-8
-244
11001
-9
-274.5
11010
-10
-305
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC register
bytes, except that the MSB of each byte functions as an enable
bit (enable = “1”). These enable bits specify which alarm
registers (seconds, minutes, etc.) are used to make the
comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the alarm
will be triggered once a match occurs between the alarm registers
and the RTC registers. Any one alarm register, multiple registers, or
all registers can be enabled for a match.
There are two alarm operation modes: Single Event and periodic
Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and
disabling the frequency output. This mode permits a one-time
match between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and the
IRQ/F_OUT output will be pulled low and will remain low until
the ALM bit is reset. This can be done manually or by using the
auto-reset feature.
• Interrupt Mode is enabled by setting the bit 7 on any of the
Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and
disabling the frequency output. The IRQ/F_OUT output will now
be pulsed each time an alarm occurs. This means that once
the interrupt mode alarm is set, it will continue to alarm for
each occurring match of the alarm and present time. This
mode is convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or utility
meter reading.
To clear a single event alarm, the ALM bit in the status register
must be set to “0” with a write. Note that if the ARST bit is set to
1 (address 08h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = “0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
ALARM
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled
HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled
DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, enabled
MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled
After these registers are set, an alarm will be generated when the
RTC advances to exactly 11:30 a.m. on January 1 (after seconds
changes from 59 to 00) by setting the ALM bit in the status register
to “1” and also bringing the IRQ/F_OUT output low.
20
FN6668.9
June 20, 2012