ISL12022MIBZ-T7A Datasheet, PDF(15/31 Page) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12022MIBZ-T7A Datasheet, PDF (15/31 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

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ISL12022M

DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)

DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the

daylight saving time forward adjustment has happened. If a DST

Forward event happens, DSTADJ will be set to â1â. The DSTADJ bit

will stay high when a DSTFD event happens, and will be reset to

â0â when the DST Reverse event happens. It is read-only and

cannot be written. Setting time during a DST forward period will

not set this bit to â1â.

The DSTE bit must be enabled when the RTC time is more than

one hour before the DST Forward or DST Reverse event time

setting, or the DST event correction will not happen.

DSTADJ is reset to â0â upon power-up. It will reset to â0â when the

DSTE bit in Register 15h is set to â0â (DST disabled), but no time

adjustment will happen.

ALARM BIT (ALM)

This bit announces if the alarm matches the real time clock. If

there is a match, the respective bit is set to â1â. This bit can be

manually reset to â0â by the user or automatically reset by

enabling the auto-reset bit (see ARST bit). A write to this bit in the

SR can only set it to â0â, not â1â. An alarm bit that is set by an

alarm occurring during an SR read operation will remain set after

the read operation is complete.

LOW VDD INDICATOR BIT (LVDD)

This bit indicates when VDD has dropped below the pre-selected trip

level (Brownout Mode). The trip points for the brownout levels are

selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in PWR_

VDD registers. The LVDD detection is only enabled in VDD mode and

the detection happens in real time. The LVDD bit is set whenever the

VDD has dropped below the pre-selected trip level, and self clears

whenever the VDD is above the pre-selected trip level.

LOW BATTERY INDICATOR 85% BIT (LBAT85)

In Normal Mode (VDD), this bit indicates when the battery level

has dropped below the pre-selected trip levels. The trip points are

selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the

PWR_VBAT registers. The LBAT85 detection happens

automatically once every minute when seconds register reaches

59. The detection can also be manually triggered by setting the

TSE bit in BETA register to â1â. The LBAT85 bit is set when the

VBAT has dropped below the pre-selected trip level, and will self

clear when the VBAT is above the pre-selected trip level at the

next detection cycle either by manual or automatic trigger.

In Battery Mode (VBAT), this bit indicates the device has entered

into battery mode by polling once every 10 minutes. The LBAT85

detection happens automatically once when the minute register

reaches x9h or x0h minutes.

Example - When the LBAT85 is Set To â1â In Battery Mode:

The minute the register changes to 19h when the device is in

battery mode, the LBAT85 is set to â1â the next time the device

switches back to Normal Mode.

Example - When the LBAT85 Remains at â0â In Battery Mode:

If the device enters into battery mode after the minute register

reaches 20h and switches back to Normal Mode before the

minute register reaches 29h, then the LBAT85 bit will remain at

â0â the next time the device switches back to Normal Mode.

LOW BATTERY INDICATOR 75% BIT (LBAT75)

In Normal Mode (VDD), this bit indicates when the battery level

has dropped below the pre-selected trip levels. The trip points are

selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the

PWR_VBAT registers. The LBAT75 detection happens

automatically once every minute when seconds register reaches

59. The detection can also be manually triggered by setting the

TSE bit in BETA register to â1â. The LBAT75 bit is set when the

VBAT has dropped below the pre-selected trip level, and will self

clear when the VBAT is above the pre-selected trip level at the

next detection cycle either by manual or automatic trigger.

In Battery Mode (VBAT), this bit indicates the device has entered

into battery mode by polling once every 10 minutes. The LBAT85

detection happens automatically once when the minute register

reaches x9h or x0h minutes.

Example - When the LBAT75 is Set to â1â in Battery Mode:

The minute register changes to 30h when the device is in battery

mode, the LBAT75 is set to â1â the next time the device switches

back to Normal Mode.

Example - When the LBAT75 Remains at â0â in Battery Mode:

If the device enters into battery mode after the minute register

reaches 49h and switches back to Normal Mode before minute

next time the device switches back to Normal Mode.

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a â1â after a total power failure. This is a read

only bit that is set by hardware (ISL12022M internally) when the

device powers up after having lost all power (defined as VDD = 0V

and VBAT = 0V). The bit is set regardless of whether VDD or VBAT

is applied first. The loss of only one of the supplies does not set

the RTCF bit to â1â. The first valid write to the RTC section after a

complete power failure resets the RTCF bit to â0â (writing one

byte is sufficient).

Interrupt Control Register (INT)

ADDR

08h

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

3210

ARST WRTC IM FOBATB FO3 FO2 FO1 FO0

AUTOMATIC RESET BIT (ARST)

This bit enables/disables the automatic reset of the ALM, LVDD,

LBAT85, and LBAT75 status bits only. When ARST bit is set to â1â,

these status bits are reset to â0â after a valid read of the

respective status register (with a valid STOP condition). When the

ARST is cleared to â0â, the user must manually reset the ALM,

LVDD, LBAT85, and LBAT75 bits.

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the RTC

Timing Registers. The factory default setting of this bit is â0â.

Upon initialization or power-up, the WRTC must be set to â1â to

enable the RTC. Upon the completion of a valid write (STOP), the

RTC starts counting. The RTC internal 1Hz signal is synchronized

to the STOP condition during a valid write cycle.

FN6668.9

June 20, 2012

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