ISL5416_14 Datasheet, PDF (59/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable

ISL5416
Electrical Specifications V_CCC = Core supply: 1.8V ± 0.09V, V_CCIO = IO’s supply: 3.3V ± 0.165V, T_A = -40^oC to 85^oC Industrial
PARAMETER
SYMBOL
MIN
MAX
UNITS
DSTRB Enable Time
DSTRB Disable Time (Note 6)
CE Setup Time to Falling Edge of DSTRB
CE Hold Time from Rising Edge of DSTRB (Note 7)
DSTRB Low Time
READ Cycle Time (Note 8)
JTAG TIMING (FIGURE 17)
t_RE
-
14
ns
t_RD
-
6.5
ns
t_CSF
7.5
-
ns
t_CHR
-2
-
ns
t_DW
5
-
ns
t_RCY
25
ns
TDI, TMS Set Up
TDI, TMS Hold
TCLK TO TDO VALID
TCLK TO TDO DISABLED
TCLK TO TDO ENABLED
CAPTURE INPUT SETUP TIME
CAPTURE INPUT HOLD TIME
TCLK TO OUTPUT VALID (Note 6)
CLOCK OUTPUT TIMING AND OUTPUT ENABLES (FIGURE 18)
TS_TT
4.5
ns
TH_TT
1.5
ns
TOV_TDO
7
ns
TOD_TDO
7
ns
TOE_TDO
7
ns
t_ISTP
5
ns
t_IHLD
1.5
ns
t_DVLD
2
6
ns
CLKC to Parallel Data, FSYNCX and CLKO1 (Divide-by 2 thru 16 Modes)
t_PD
2
6.5
ns
(NOTE 6)
CLKC Low to CLKO1 Low (Divide-by 1 Mode)
t_PDL
2
6.5
ns
(NOTE 6)
CLKC High to CLKO1 High (Divide-by 1 Mode)
t_PDH
2
6.5
ns
(NOTE 6)
Time Skew Between CLKO1 and Parallel Data or FSYNCX (Divide-by 2 thru 16 Modes)
t_SKEW3
-1.5
1.5
ns
Time Skew Between CLKO1 and Parallel Data or FSYNCX (Divide-by 1 Mode)
t_SKEW4
-2.5
1.5
ns
OUTPUT ENABLE TIME
t_OEN
6
ns
OUTPUT DISABLE TIME
t_ODIS
4
ns
NOTES:
5. The ISL5416 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
7. t_AHR and t_CHR apply ONLY to direct reads of addresses 4 - 7.
8. Reading from direct addresses 4 - 7 (Sequential Read Mode).
AC Test Load Circuit
DUT
S₁
C_L (NOTE)
NOTE - TEST HEAD CAPACITANCE, 50pF (TYP)
SWITCH S1 OPEN FOR I_CCSB AND I_CCOP
±
I_OH
1.5V
I_OL
EQUIVALENT CIRCUIT
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