ISL5416_14 Datasheet, PDF (58/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable

ISL5416
Electrical Specifications V_CCC = Core supply: 1.8V ± 0.09V, V_CCIO = IO’s supply: 3.3V ± 0.165V, T_A = -40^oC to 85^oC Industrial
PARAMETER
SYMBOL
MIN
MAX
UNITS
INPUT AND CONTROL TIMING, CLOCK SKEW (FIGURE 11 AND 12)
CLKC Frequency
CLKC High
CLKC Low
Setup Time - Data Inputs, Input Enables to CLKX High
Hold Time - Data Inputs, Input Enables to CLKX High
Setup Time - SYNCInX to CLKC High
Hold Time - SYNCInX to CLKC High
CLKC to Output Valid - SYNCO
RESET Pulse Width Low
RESET Setup Time to CLKC High (Note 5)
CLKX to CLKC skew 1 (FIGURE 12)
CLKX to CLKC skew 2 (FIGURE 12)
MICROPROCESSOR WRITE TIMING (µP mode = 0, FIGURE 13)
f_CLK
-
t_CH
3
t_CL
4
t_DS
5.5
t_DH
0
t_SYNCS
3
t_SYNCH
0
t_PDC
-
t_RW
5
t_RS
5
t_CKS1
2.5
t_CKS2
2.5
95
MHz
-
ns
-
ns
-
ns
-
ns
5
ns
-
ns
-
ns
P(15:0) Setup Time to Rising Edge of WR
P(15:0) Hold Time from Rising Edge of WR
A(2:0) Setup Time to Rising Edge of WR
A(2:0) Hold Time from Rising Edge of WR
CE Setup Time to Rising Edge of WR
CE Hold Time from Rising Edge of WR
WR Low Time
MICROPROCESSOR READ TIMING (µP mode = 0, FIGURE 14)
t_PSW
7.5
-
ns
t_PHW
-1
-
ns
t_ASW
8.5
-
ns
t_AHW
-2
-
ns
t_CSW
7
-
ns
t_CHW
-2
-
ns
t_WPWL
5
-
ns
A(2:0) Hold Time from RISING Edge of RD (Note 7)
A(2:0) to P(15:0) Data Valid Time
RD Enable Time
RD Disable Time (Note 6)
CE Setup Time to Falling Edge of RD
CE Hold Time from Rising Edge of RD (Note 6)
READ Cycle Time (Note 7)
MICROPROCESSOR WRITE TIMING (µP MODE = 1, FIGURE 15)
t_AHR
-4
-
ns
t_DV
-
19
ns
t_RE
-
8.5
ns
t_RD
-
6
ns
t_CSF
2.5
-
ns
t_CHR
0
-
ns
t_RCY
25
-
ns
P(15:0) Setup Time to Rising Edge of DSTRB
P(15:0) Hold Time from Rising Edge of DSTRB
A(2:0) Setup Time to Rising Edge of DSTRB
A(2:0) Hold Time from Rising Edge of DSTRB
CE Setup Time to Rising Edge of DSTRB
CE Hold Time from Rising Edge of DSTRB
R/W Setup Time to Falling Edge of DSTRB
R/W Hold Time from Rising Edge of DSTRB
DSTRB Low Time
MICROPROCESSOR READ TIMING (µP MODE = 1, FIGURE 16)
t_PSR
8
-
ns
t_PHR
-0.5
-
ns
t_ASR
7.5
-
ns
t_AHR
-1.5
-
ns
t_CSR
8
-
ns
t_CHR
-2
-
ns
t_R/WSF
0
-
ns
t_R/WHR
-1
-
ns
t_DW
6
-
ns
A(2:0) Hold Time from RISING Edge of DSTRB (Note 7)
A(2:0) to P(15:0) Data Valid Time
t_AHR
-1
-
ns
t_DV
-
16
ns
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