X96011_08 Datasheet, PDF (5/18 Pages) Intersil Corporation – Temperature Sensor with Look-Up Table Memory and DAC

X96011
2-Wire Interface AC Characteristics (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNITS
t_SU:DAT
Data In Setup Time
See Table 2-Wire Interface Test
100
ns
Conditions on page 5
t_HD:DAT
t_SU:STO
t_DH
t_R
(Note 11)
t_F
(Note 11)
t_SU:WP
(Note 11)
t_HD:WP
(Note 11)
Cb
(Note 11)
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
Sda And Scl Rise Time
Sda And Scl Fall Time
Wp Setup Time
Wp Hold Time
Capacitive Load For Each Bus Line
(Figure 1, 2 and 3)
0
600
50
20 + 0.1Cb
(Note 8)
20 + 0.1Cb
(Note 8)
600
600
µs
ns
ns
300
ns
300
ns
ns
ns
400
pF
2-Wire Interface Test Conditions
Input Pulse Levels
Input Rise and Fall Times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at pin SDA
10% to 90% of V_CC
10ns
1.4V
2.3kΩ to V_CC and 100pF to V_SS
Nonvolatile WRITE Cycle Timing
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
t_WC
(Note 9)
Nonvolatile Write Cycle Time
See Figure 3
5
10
ms
NOTES:
8. Cb = total capacitance of one bus line (SDA or SCL) in pF.
9. t_WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
10. The minimum frequency requirement applies between a START and a STOP condition.
11. These parameters are periodically sampled and not 100% tested.
Timing Diagrams
SCL
t_SU:STA
SDA IN
SDA OUT
t_F
t_SU:DAT
t_HD:STA
t_HIGH
t_LOW
t_R
t_HD:DAT
t_AA
t_DH
t_SU:STO
t_BUF
FIGURE 1. BUS TIMING
5
FN8215.2
February 25, 2008