X96011_08 Datasheet, PDF (15/18 Pages) Intersil Corporation – Temperature Sensor with Look-Up Table Memory and DAC

X96011
BYTE LOAD COMPLETED BY
ISSUING STOP. ENTER ACK POLLING
ISSUE “START”
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
ISSUE “STOP”
NO
ACK RETURNED?
YES
HIGH VOLTAGE
NO
COMPLETE. CONTINUE COMMAND
SEQUENCE.
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 9.
For any Byte Write operation, the X96011 requires the Slave
Address Byte, an Address Byte, and a Data Byte (See Figure
15). After each of them, the X96011 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if all data bits are volatile, the
X96011 is ready for the next read or write operation. If some
bits are nonvolatile, the X96011 begins the internal write cycle
to the nonvolatile memory. During the internal nonvolatile write
cycle, the X96011 does not respond to any requests from the
master. The SDA output is at high impedance.
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in the section
“Writing to Control Registers” .
YES
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
ISSUE “STOP”
PROCEED
FIGURE 14. ACKNOWLEDGE POLLING SEQUENCE
SIGNALS FROM
the MASTER
WRITE
S
T
A
SLAVE
R
ADDRESS
T
ADDRESS
BYTE
DATA
BYTE
S
T
O
P
SIGNAL AT SDA
10 10
0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 15. BYTE WRITE SEQUENCE
15
FN8215.2
February 25, 2008