X96011_08 Datasheet, PDF (14/18 Pages) Intersil Corporation – Temperature Sensor with Look-Up Table Memory and DAC

X96011
ADDRESS
SIZE
CFh
LOOK-UP TABLE
(LUT)
90h
8Fh
CONTROL AND STATUS
REGISTERS
80h
64 Bytes
16 Bytes
FIGURE 12. X96011 MEMORY MAP
X96011 Memory Map
The X96011 contains a 80 byte array of mixed volatile and
nonvolatile memory. This array is split up into two distinct
parts, namely: (Refer to Figure 12).
• Look-up Table (LUT)
• Control and Status Registers
The Control and Status registers of the X96011 are used in
the test and setup of the device in a system. These registers
are realized as a combination of both volatile and nonvolatile
memory. These registers reside in the memory locations 80h
through 8Fh. The reserved bits within registers 80h through
86h, must be written as “0” if writing to them, and should be
ignored when reading. Register bits shown as 0 or 1, in
Figure 4, must be written with the indicated value if writing to
them. The reserved registers, 82h, 84h, and from 88h
through 8Fh, must not be written, and their content should
be ignored.
The LUT is realized as nonvolatile EEPROM, and extend
from memory locations 90h–CFh. This LUT is dedicated to
storing data solely for the purpose of setting the outputs of
Current Generators I_OUT.
All bits in the LUT are preprogrammed to “0” at the factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START,
followed by a Slave Address Byte. The Slave address
selects the X96011, and specifies if a Read or Write
operation is to be performed.
It should be noted that the Write Enable Latch (WEL) bit
must first be set in order to perform a Write operation to any
other bit. See “WEL: Write Enable Latch (Volatile)” on
page 9. Also, all communication to the X96011 over the
2-wire serial bus is conducted by sending the MSB of each
byte of data first.
The memory is physically realized as one contiguous array,
organized as 5 pages of 16 bytes each.
The X96011 2-wire protocol provides one address byte. The
next few sections explain how to access the different areas
for reading and writing.
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
1
0
1
0 AS2 AS1 AS0 R/W
Device Type
Identifier
SLAVE ADDRESS
BIT(s)
SA7 - SA4
SA3 - SA1
Device
Address
Read or
Write
DESCRIPTION
Device Type Identifier
Device Address
FIGURE 13. SLAVE ADDRESS (SA) FORMAT
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 13). This byte includes
three parts:
• The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96011.
• The next three bits (SA3 - SA1) are the Device Address
bits (AS2 - AS0). To access any part of the X96011’s
memory, the value of bits AS2, AS1, and AS0 must
correspond to the logic levels at pins A2, A1, and A0
respectively.
• The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being addressed.
When the R/W bit is “1”, then a Read operation is
selected. A “0” selects a Write operation
(Refer to Figure 13)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96011
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96011. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96011’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. (Refer to Figure 14)
14
FN8215.2
February 25, 2008