X96011_08 Datasheet, PDF (16/18 Pages) Intersil Corporation – Temperature Sensor with Look-Up Table Memory and DAC

X96011
Page Write Operation
The 80-byte memory array is physically realized as one
contiguous array, organized as 5 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the four
LUT pages. In order to perform a Page Write operation, the
Write Enable Latch (WEL) bit in Control register 6 must first
be set (See “WEL: Write Enable Latch (Volatile)” on page 9.)
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (See Figure 16). After the receipt of
each byte, the X96011 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
For example, if the master writes 12 bytes to a 16-byte page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6 within that page. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time.
(See Figure 17).
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle.
A Page Write operation cannot be performed on the page at
locations 80h through 8Fh. The next section describes the
special cases within that page.
Writing to Control Registers
The bytes at locations 80h, 81h, 83h, 85h, and 86h are
written using Byte Write operations. They cannot be written
using a Page Write operation.
Registers Control 1 and 3 have a nonvolatile and a volatile cell
for each bit. At power-up, the content of the nonvolatile cells is
automatically recalled and written to the volatile cells. The
content of the volatile cells controls the X96011’s functionality.
If bit NV13 in the Control 0 register is set to “1”, a Write
operation to these registers writes to both the volatile and
nonvolatile cells. If bit NV13 in the Control 0 register is set to
“0”, a Write operation to these registers only writes to the
volatile cells. In both cases the newly written values effectively
control the X96011, but in the second case, those values are
lost when the part is powered down.
If bit NV13 is set to “0”, a Byte Write operation to Control
registers 0 or 5 causes the value in the nonvolatile cells of
Control registers 1 and 3 to be recalled into their
corresponding volatile cells, as during power-up. This
doesn’t happen when the WP pin is LOW, because Write
Protection is enabled. It is generally recommended to
configure Control registers 0 and 5 before writing to Control
registers 1 or 3.
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
WRITE
S
T
A
SLAVE
R
ADDRESS
T
ADDRESS
BYTE
2 < n < 16
DATA BYTE (1)
S
T
DATA BYTE (n)
O
P
10 10
0
A
A
C
C
K
K
A
A
C
C
K
K
FIGURE 16. PAGE WRITE OPERATION
7 BYTES
5 b5yBtYeTsES
ADDRESS = 0
ADDRESS = 6
ADDRESS = 11
ADDRESS = 7
ADDRESS POINTER
ENDS UP HERE
ADDRESS = 15
FIGURE 17. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
16
FN8215.2
February 25, 2008