X9119 Datasheet, PDF (5/18 Pages) Xilinx, Inc – Single Digitally-Controlled (XDCP ™ ) Potentiometer

X9119
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Figure 2. Acknowledge Response from Receiver
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.
SCL from
Master
1
Data Output
from Transmitter
8
9
Data Output
from Receiver
START
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9119 is still busy with the write operation no ACK
will be returned. If the X9119 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
ACKNOWLEDGE
FLOW 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
Issue STOP
ACK
No
Returned?
Yes
Further
No
Operation?
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
5
FN8162.2
September 15, 2005