X9119 Datasheet, PDF (13/18 Pages) Xilinx, Inc – Single Digitally-Controlled (XDCP ™ ) Potentiometer

X9119
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
SDA OUTPUT
5V
1533Ω
100pF
SDA OUTPUT
3V
867Ω
100pF
SPICE Macromodel
R_TOTAL
R_H
R_L
C_L
C_W
C_L
10pF
10pF
25pF
R_W
AC TIMING HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
f_SCL
t_CYC
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:STO
t_SU:DAT
t_HD:DAT
t_R
t_F
t_AA
t_DH
T_I
t_BUF
t_SU:WPA
t_HD:WPA
Parameter
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Setup Time
Start Hold Time
Stop Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 Setup Time
A0, A1, A2 Hold Time
Min.
2500
600
1300
600
600
600
100
0
250
0
50
1300
0
0
Max.
400
300
300
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
FN8162.2
September 15, 2005