X9119 Datasheet, PDF (4/18 Pages) Xilinx, Inc – Single Digitally-Controlled (XDCP ™ ) Potentiometer

X9119
Resistor Array Description
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R_H and R_L
inputs).
Figure 1. Detailed Potentiometer Block Diagram
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R_W) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
Serial Data Path
Serial
RH
From Interface
Circuitry
Bus
Input
Register 0
Register 1
C
(DR0)
(DR1)
O
U
10
10 Parallel
Bus
Input
N
T
E
R
Register 2
(DR2)
Register 3
(DR3)
Wiper
D
Counter
E
Register
C
(WCR)
O
D
E
If WCR = 000[HEX] then R_W = R_L
If WCR = 3FF[HEX] then R_W = R_H
RL
RW
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 3.
STOP CONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
ACKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
4
FN8162.2
September 15, 2005