X80000 Datasheet, PDF (5/37 Pages) Intersil Corporation – Smart Power Plug Penta-Power Sequence Controller with Hot Swap

X80000, X80001
Electrical Specifications Standard Settings
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
t_MRHD
t_{RESET_E}
Delay from MRH disable to GATE reaching 1V
Delay from PWRGD or ViGOOD to RESET valid
LOW
I_GATE = 60µA, No Load
t_QC
Delay from IGQ1 and IGQ0 to valid Gate pin
current
t_{SC_RETRY} Delay between retries
TSC1 = 0; TSC0 = 0
t_NF
Noise Filter for Overcurrent
TF1 = 0; TF0 = 1
t_DPOR Device Delay before Gate assertion
t_SPOR
Delay after PWRGD and all ViGOOD signals are TPOR1 = 0; TPOR0 = 0
active before RESET assertion
t_TO
t_PDHLPG
(Note 1)
ViGOOD turn off time
Delay from Drain good to PWRGD LOW
Gate = V_DD
t_PDLHPG Delay from Drain fail to PWRGD HIGH
(Note 1)
Gate = V_DD
t_PGHLPG Delay from Gate good to PWRGD LOW
(Note 1)
Drain = V_EE
t_PGLHPG Delay from Gate fail to PWRGD HIGH
(Note 1)
Drain = V_EE
NOTE:
1. This parameter is based on characterization data.
Equivalent A.C. Output Load Circuit
5V
5V
5V
SDA
4.6kΩ
30pF
RESET
FAR
PWRGD
4.6kΩ
30pF
V1GOOD,
V2GOOD,
V3GOOD,
V4GOOD,
4.6kΩ
30pF
MIN
TYP
MAX
UNIT
1.8
2.6
µs
1
µs
1
µs
90
100
110
ms
4.5
5
5.5
µs
45
50
55
ms
90
100
110
ms
50
ns
1
µs
1
µs
1
µs
1
µs
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
Standard output load
5
FN8148.0
March 18, 2005