X80000 Datasheet, PDF (10/37 Pages) Intersil Corporation – Smart Power Plug Penta-Power Sequence Controller with Hot Swap

X80000, X80001
Serial Interface (Continued)
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t_BUF
Time the bus is free before start of new
transmission
1.3
µs
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
(Note 1)
µs
µs
µs
µs
ns
µs
µs
ns
300
ns
t_F
SDA and SCL Fall Time
20 +.1Cb
(Note 1)
300
ns
t_SU:WP
t_HD:WP
Cb
WP Setup Time
WP Hold Time
Capacitive load for each bus line
0.6
µs
0
µs
400
pF
t_WC (Note 2) EEPROM Write Cycle Time
5
10
ms
NOTE:
2. t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Timing Diagrams
t_BUF
SCL
t_SU:STA
SDA IN
t_F
t_SU:DAT
t_HD:STA
SDA OUT
t_HIGH
t_LOW
t_R
t_HD:DAT
t_SU:STO
t_AA t_DH
FIGURE 7. BUS TIMING
t_BUF
t_HD:STO
t_HD:DAT
10
FN8148.0
March 18, 2005