X80000 Datasheet, PDF (21/37 Pages) Intersil Corporation – Smart Power Plug Penta-Power Sequence Controller with Hot Swap

X80000, X80001
operation to control Inrush currents during hot insertion
modes.
V_DD=12V
10µA
to
160µA
Slew
Rate
Selection
Logic
Gate Current
Quick Select
Logic
Control
Registers
V_EE SENSE GATE
DRAIN
SMBus
IGQ1
IGQ0
SCL
SDA
100nF*
100*
R2
22K
C2
3.3nF
100K
-48V
R_SENSE
I_INRUSH
LOAD
* Optional Components
See Section “Gate Capacitor, Filtering and Feedback”
FIGURE 29. PROGRAMMBLE SLEW RATE (INRUSH
CURRENT) CONTROL
Software Slew Rate Control
Users can adjust the slew rate control by using an SMBus
write command to change the slew rate control bits. This
allows adaptation in the case of changing load conditions,
creates a modular design for downstream DC-DC supplies,
and provides control of the load on the hot voltage when
slew rates vs. loads vary.
Gate Capacitor, Filtering and Feedback
In Figure 29, the FET control circuit includes an FET
feedback capacitor C₂, which provides compensation for the
FET during turn on. The capacitor value depends on the
load, the FET gate current, and the maximum desired inrush
current.
The value of C2 can be selected with the following formula:
C2 = ^I--G-----^A----^T---^E-----^×-----C-----^L---^O-----^A---^D---
I_INRUSH
Where:
I_GATE = FET Gate current
I_INRUSH = Maximum desired inrush current
C_LOAD = DC/DC bulk capacitance
With the X80000, there is some control of the gate current
with the IGQ pins and IGx bits, so one selection of C2 can
cover a wide range of possible loading conditions. Typical
values for C2 range from 2.2 to 4.7nF.
When power is applied to the system, the FET tries to turn
on due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 29). The X80000 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on.
However, unless V_DD powers up very quickly, there will be a
brief period of time during initial application of power when
the X80000 circuits cannot hold the gate low. The use of an
external capacitor (C1) prevents this. Capacitors C1 and C2
form a voltage divider to prevent the gate voltage from rising
above the FET turn on threshold before the X80000 can hold
the gate low. Use the following formula for choosing C1.
C1 = ^{V-----1-----–}----V-----2--C2
V2
Where:
V1 = Maximum input voltage,
V2 = FET threshold Voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.
In a system where V_DD rises very fast, a smaller value of C1
may suffice as the X80000 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 29 assumes that the input voltage can rise to
80V before the X80000 sees operational voltage on V_DD. If
C1 is used then the series resistor R1 will be required to
prevent high frequency oscillations.
TABLE 10. I_GATE OUTPUT CURRENT OPTIONS
IG3
IG2
IG1
IG0
I_GATE (µA)
0
0
0
0
10
0
0
0
1
20
0
0
1
0
30
0
0
1
1
40
0
1
0
0
50
Default
0
1
0
1
60
0
1
1
0
70
0
1
1
1
80
1
0
0
0
90
1
0
0
1
100
1
0
1
0
110
1
0
1
1
120
1
1
0
0
130
1
1
0
1
140
1
1
1
0
150
1
1
1
1
160
GATE Current Quick Selection
For applications that require different ramp rates during
insertion and start-up and operations modes or those where
the serial interface is not available, the X80000 provides two
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FN8148.0
March 18, 2005