X80000 Datasheet, PDF (24/37 Pages) Intersil Corporation – Smart Power Plug Penta-Power Sequence Controller with Hot Swap

X80000, X80001
gate will turn on based on the selected gate control
mechanism.
TABLE 13. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL)
MRH GATE PIN
REQUIREMENTS
1 Operational When MRH is HIGH the Manual Reset (Hot)
function is disabled and the
device operates normally
0
OFF
MRH must be held LOW minimum of 5µsecs
to turn of the GATE
The MRC signal is used as a manual reset for the PWRGD
signal. This pin is used to initiate a Soft Restart. When the
MRC is pulled HIGH, the PWRGD signal is pulled HIGH.
When MRC pin goes LOW, the PWRGD pin goes low using
the MRC pin has no affect on the FET gate control, so the
FET remains on.
TABLE 14. MANUAL RESET OF THE COLD SIDE (PWRGD
SIGNAL)
MRC PWRGD
Requirements
1
HIGH MRC must be held HIGH minimum of 5µsecs
to set PWRGD HIGH
0 Operational When MRC is LOW the MRC function is
disabled and the device operates normally
Fault Detection
The X80000 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET pin
active (See Table 17).
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize the register to all “1” before the actual
monitoring can take place. In the event that any one of the
monitored sources fail, the corresponding bit in the register
changes from a “1” to a “0” to indicate the failure (ViGOOD
sources set the bit LOW when the ViGOOD goes LOW
indicating a “good” status). When a RESET is detected by
the main controller, the controller should read of the FDR
and note the cause of the fault. After reading the register, the
controller can reset the register bit back to all “1” in
preparation for future monitored conditions.
Remote Shutdown
The gate of the external MOSFET can be remotely shutdown
by using a software command sequence. A byte write of
‘10101010’ (AAh) data to the Remote Shutdown Register
(RSR) will shutdown the gate and the gate will be pulled low.
Activating the MRH pin or a writing 00h into the RSR will turn
off the override signal and the gate will turn on based on the
gate control mechanism.
The RSR powers up with ‘0’s in the register and its contents
are volatile.
Flexible Power Sequencing of Multiple Power
Supplies
The X80000 provides several circuits such as multiple
voltage enable pins, programmable delays, and a power
good signals that can be used to set up flexible power
sequencing schemes for downstream DC-DC supplies.
Below are two examples:
1. Power Up of DC-DC Supplies In Parallel Sequencing
Using Programmable Delays on Power Good (See Figure
33 and Figure 34).
Several DC-DC power supplies and their respective
power up start times can be controlled using the X80000
such that each of the DC-DC power supplies will start up
following the issue of the PWRGD signal. The PWRGD
signal is fed into the ENi inputs to the X80000. When
PWRGD is valid, the internal voltage enable inputs issue
ViGOOD signals after a time delay. The ViGOOD signals
control the ON/OFF pins of the DC-DC supplies. In the
factory default condition, each DC/DC converter is
instructed to turn on 100ms after the PWRGD goes
active. However, each ViGOOD delay is individually
selectable as 100ms, 500ms, 1s and 5s. The delay times
are changed via the SMBus during calibration of the
system.
2. Power Up of DC-DC Supplies Via Relay Sequencing
Using Power Good and Voltage Enables (see Figure 35
and Figure 36).
Several DC-DC power supplies and their respective
power up start times can be controlled using the X80000
such that each of the DC-DC power supplies will start in
a relay sequencing fashion. The 1st DC-DC supply will
power up when PWRGD is LOW after a 100ms delay.
Subsequent DC-DC supplies will power up after the prior
supply has reached its operating voltage. One way to do
this is by using an external CPU Supervisor (for example
the Intersil X40430) to monitor the DC-DC output. When
the DC/DC voltage is good, the supervisor output signals
the X80000 EN1 input to sequence the next supply. An
opto-coupler is recommended in this connection for
isolation. This configuration ensures that each
subsequent DC-DC supply will power up after the
preceding DC-DC supplys voltage output is valid. Again,
the X80000 offers programmable delays for each voltage
enable input that is selectable via the SMBus during
calibration of the system.
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FN8148.0
March 18, 2005