X80000 Datasheet, PDF (19/37 Pages) Intersil Corporation – Smart Power Plug Penta-Power Sequence Controller with Hot Swap

X80000, X80001
Programmable
Voltage Reference
36R
R
3x ^4x
R _2x
R
1x
R
2 bit
0µs
noise 5µs
filtering 10µs
20µs
–
+
Overcurrent
Logic and Gate
Control Block
Fault Bit
FAR_STAT
Short-Circuit
Retry Logic
and System
Monitors
Retry Delay
Retry Counter
N_retry
Failure After
Re-Try
FAR
V_EE
Control
Registers
SMBus
SCL
SDA
-48V
R_Sense
Overcurrent Event
FIGURE 27. OVERCURRENT DETECTION/SHORT CIRCUIT PROTECTION WITH PROGRAMMBLE RETRY AND FLAG MONITORS
Overcurrent During Insertion
Insertion is defined as the first plug-in of the board to the
backplane. In this case, the X80000 is initially fully powered
off prior to the hot plug connection to the mains supply. This
condition is different from a situation where the mains supply
has temporarily failed resulting in a partial recycle of the
power. This second condition will be referred to as a power
cycle.
During insertion, the board can experience high levels of
current for short periods of time as power supply capacitors
charge up on the power bus. To prevent the overcurrent
sensor from turning off the FET inadvertently, the X80000
has the ability to allow more current to flow through the
powerFET and the sense resistor for a short period of time
until the FET turns on and the PWRGD signal goes active. In
the standard setting, 200mV is allowed across sense resistor
the during insertion (10A assuming a 20mW resistor). Two
bits in register CR4 select the insertion current limit of 1X,
2X, 3X or 4X the base setting of 50mV. This provides a
mechanism to reduce insertion issues associated with huge
current surges.
TABLE 5. INSERTION OVERCURRENT THRESHOLD OPTIONS
VS1
VS0
0
0
V_OCI
50mV (1X)
0
1
100mV (2X)
1
0
150mV (3X)
1
1
200mV (4X)
Hardshort Protection - Programmable Retry
In the event on an overcurrent or hard short condition, the
X80000 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition
still exists, the FET turns off and a retry counter
(SC_Counter) increments. After the selected number of
failed trys, the X80000 sets a Failed After Retry Status
(FAR_STAT) fault bit, sets the FAR pin LOW and goes into
an idle state. In this state the GATE pin will not go active until
the device is cleared.
The retry circuit can be programmed to handle the retry
operation in one of eight ways (See Table 6). The options
allow retries from zero to unlimited and specifies when to
assert the FAR (Failure After Re-Try) signal. In the “Always
Retry” case there is no idle state, so when the overcurrent
condition clears, the GATE goes active and the FET turns
on.
There are four optional retry delay periods. These are
100ms, 500ms, 1s, and 5s. These are programmed by bits
located in the CR2 register.
After FAR is asserted, there are two ways to clear the
hardshort protection:
1. Master Reset Hot Side. The master reset pin, MRH, can
be asserted by pulling it LOW. Upon MRH assertion, all
default values are restored and the retry is cleared.
2. Power cycle the part, turning V_DD OFF, then ON.
If an overcurrent condition does not occur on any retry, the
gate pin will proceed to open at the user defined slew rate.
Overcurrent Fault Condition Flags
On any overcurrent violation, the X80000 will cut-off the
GATE, turning off the voltage to the load, and setting all
power good pins to their disabled state. In this condition, the
fault-overcurrent bit (FOC) goes LOW. To clear FOC,
remove the over current condition, then write to the control
register. Refer to instructions on writing to the FDR (See
Table 8).
19
FN8148.0
March 18, 2005