ISL12026 Datasheet, PDF (5/24 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12026
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS NOTES
t_HD:STO STOP Condition Hold Time for
From SDA rising edge to SCL
600
Read, or Volatile Only Write
falling edge. Both crossing 70%
of V_DD.
t_DH
Output Data Hold Time
From SCL falling edge crossing
0
30% of V_DD, until SDA enters the
30% to 70% of V_DD window.
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip.
10
ns
ns
400
pF
Cpin SDA, and SCL Pin Capacitance
10
pF
t_WC Non-volatile Write Cycle Time
12
20
ms
10
NOTES:
3. IRQ/F_OUT Inactive.
4. V_IL = V_DD x 0.1, V_IH = V_DD x 0.9, f_SCL = 400kHz
5. V_DD > V_BAT +V_BATHYS
6. Bit BSW = 0 (Standard Mode), V_BAT >= 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V_{DD SR-} specification must be followed.
9. Parameter is not 100% tested.
10. t_WC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
Timing Diagrams
Bus Timing
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_R
t_HD:DAT
t_AA
t_DH
t_HD:STO
t_SU:STO
t_BUF
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
t_WC
STOP
CONDITION
START
CONDITION
5
FN8231.5
October 23, 2006