ISL12026 Datasheet, PDF (10/24 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12026
ADDR.
TYPE
REG
NAME
003F
Status
SR
0037
RTC
Y2K
0036 ^(SRAM)
DW
0035
YR
0034
MO
0033
DT
0032
HR
0031
MN
0030
SC
0014 Control PWR
0013 ^(EEPROM) DTR
0012
ATR
0011
INT
0010
BL
000F Alarm1 Y2K1
000E ^(EEPROM) DWA1
000D
YRA1
000C
MOA1
000B
DTA1
000A
HRA1
0009
MNA1
0008
SCA1
0007 Alarm0 Y2K0
0006 ^(EEPROM) DWA0
0005
YRA0
0004
MOA0
0003
DTA0
0002
HRA0
0001
MNA0
0000
SCA0
7
BAT
0
0
Y23
0
0
MIL
0
0
SBIB
0
0
IM
BP2
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
TABLE 2. CLOCK/CONTROL MEMORY MAP
BIT
6
5
4
3
2
1
0
RANGE
AL1
0
0
Y22
0
0
0
M22
S22
BSW
0
0
AL1E
BP1
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
0
ATR5
AL0E
BP0
OSCF
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
0
ATR4
FO1
0
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
0
ATR3
FO0
0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
0
DTR2
ATR2
0
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
0
DTR1
ATR1
0
0
RTCF
01h
Y2K10 19/20 20h
DY0
0-6 00h
Y10
0-99 00h
G10
1-12 00h
D10
1-31 01h
H10
0-23 00h
M10
0-59 00h
S10
0-59 00h
0
40h
DTR0
00h
ATR0
00h
0
00h
0
00h
0
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20 20h
0
0
0
0
DY2
DY1
DY0
0-6 00h
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h
0
A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h
0
A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h
0
A0Y2K21 A0Y2K20 A0Y2K13
0
0
A0Y2K10 19/20 20h
0
0
0
0
DY2
DY1
DY0
0-6 00h
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h
0
A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h
0
A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See the Device Operation and
Application section for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
10
FN8231.5
October 23, 2006