ISL12026 Datasheet, PDF (2/24 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

Block Diagram
ISL12026
OSC
COMPENSATION
X1
32.768kHz
X2
IRQ/F_OUT
SELECT
OSCILLATOR
FREQUENCY 1Hz
DIVIDER
TIMER
CALENDAR
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
V_DD
V_BAT
SCL
SDA
SERIAL
INTERFACE
DECODER
CONTROL
DECODE
LOGIC
CONTROL/
REGISTERS
(EEPROM)
8
STATUS
REGISTERS
(SRAM)
ALARM
COMPARE
ALARM REGS
(EEPROM)
4K
EEPROM
ARRAY
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
1
3
2
4
3
5
SYMBOL
DESCRIPTION
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. (See Application Section)
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. (See Application Section)
IRQ/F_OUT Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency
output pin. The function is set via the control register. This output is an open drain configuration.
4
6
GND Ground.
5
7
SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open
drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
7
1
V_BAT
This input provides a backup supply voltage to the device. V_BAT supplies power to the device in the event
that the V_DD supply fails. This pin should be tied to ground if not used.
8
2
V_DD
Power Supply.
2
FN8231.5
October 23, 2006