ISL12026 Datasheet, PDF (17/24 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12026
S
SIGNALS FROM
THE MASTER
T
A
R
SLAVE
T
ADDRESS
WORD
ADDRESS 1
WORD
ADDRESS 0
1 ≤ n ≤ 16 for EEPROM array
1 ≤ n ≤ 8 for CCR
DATA
(1)
S
DATA
(n)
T
O
P
SDA BUS
1
1 1 10 000 00 0 0
A
A
A
A
SIGNALS FROM
C
C
C
C
THE SLAVE
K
K
K
K
FIGURE 17. PAGE WRITE SEQUENCE
After the receipt of each byte, the ISL12026 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time. Refer to Figure 18. The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12026 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 17 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12026 resets itself without performing the write. The
contents of the array are not affected.
.
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12026 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12026 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12026 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 20. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12026 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power up, the sixteen bit address is initialized to 00h. In this
way, a current address read immediately after the power on
reset can download the entire contents of memory starting at
the first location.Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12026 issues an
acknowledge, then transmits eight data bits. The master
terminates the read operation by not responding with an
6 BYTES
6 BYTES
ADDRESS = 5
ADDRESS POINTER ENDS
AT ADDR = 5
ADDRESS
10
ADDRESS
15
FIGURE 18. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
17
FN8231.5
October 23, 2006