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| ISL12026 Datasheet, PDF (4/24 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM | |||
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ISL12026
EEPROM Specifications
SYMBOL
PARAMETER
EEPROM Endurance
EEPROM Retention
TEST CONDITIONS
Temperature â¤75°C
MIN
TYP
>2,000,000
50
MAX
UNITS
Cycles
Years
NOTES
Serial Interface (I2C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
VIL
SDA, and SCL Input Buffer LOW
Voltage
VIH
SDA, and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL SDA Output Buffer LOW Voltage IOL = 4mA
ILI
Input Leakage Current on SCL
VIN = 5.5V
ILO
I/O Leakage Current on SDA
VIN = 5.5V
MIN
TYP
MAX
UNITS NOTES
-0.3
0.3 x VDD
V
0.7 x VDD
VDD + 0.3
V
0.05 x VDD
V
0
0.4
V
100
nA
100
nA
AC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
fSCL SCL Frequency
tIN
Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed.
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
tLOW Clock LOW Time
Measured at the 30% of VDD
crossing.
tHIGH Clock HIGH Time
Measured at the 70% of VDD
crossing.
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
From SDA exiting the 30% to
70% of VDD window, to SCL rising
edge crossing 30% of VDD.
From SCL rising edge crossing
70% of VDD to SDA entering the
30% to 70% of VDD window.
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
MIN
1300
1300
600
600
600
100
0
600
TYP
MAX
400
50
900
UNITS
kHz
ns
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
FN8231.5
October 23, 2006
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