ISL6333_14 Datasheet, PDF (35/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
In Equation 40, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V_P-P is the
peak-to-peak sawtooth signal amplitude, as described in the
“Electrical Specifications” on page 13.
Once selected, the compensation values in Equation 40
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 40 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 24). Keep
a position available for C₂, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C
=
R_FB
⋅
2-----⋅_---π_-----⋅_---f--0----⋅_{---V-----P------P-----}⋅_{-------L-----}⋅_---C---
V_IN
C_C
=
-----------------------V----^I--^N------------------------
2 ⋅ π ⋅ V_P-P ⋅ R_FB ⋅ f₀
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
2-----⋅^---π^-----⋅^---C--1----⋅^{---E----S-----R---}
R_C
=
R_FB
⋅
V-----_P----P-----⋅_---(_--2-----⋅_---π_----)_--²_----⋅_-----f-0--²_-----⋅_---L-----⋅_---C---
V_IN
C_C
=
---------------------------------------V----^I--^N-----------------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_P-P ⋅ R_FB ⋅ L ⋅ C
(EQ. 40)
Case 3:
f₀
>
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C
=
R_FB
⋅
-2----^â‹---^π------^â‹---f--⁰----^â‹---V----^P----^---^P-----^â‹---L-
V_IN ⋅ ESR
C_C
=
-------------V----^I--^N------^â‹---E----S-----R-----^â‹--------C---------------
2 ⋅ π ⋅ V_P-P ⋅ R_FB ⋅ f₀ ⋅ L
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 25, provides the
necessary compensation.
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6333
VSEN
FIGURE 25. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
R₁
=
R_FB
⋅ ------------C------^â‹---E----S-----R-------------
L ⋅ C – C ⋅ ESR
C₁
=
-----L-----^â‹---C-----^–-----C------^â‹---E----S-----R--
R_FB
C₂
=
----------------------------------------------V-----^I--^N------------------------------------------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
R_C
=
-V----^P----^P-----^â‹---^⎝⎛---2----^π---^⎠⎞---²-----^â‹---f--⁰----^â‹---f--^H----^F-----^â‹---L-----^â‹---C-----^â‹---R-----^F----^B--
V_IN ^{⋅ (2 ⋅ π ⋅ f}_HF ^{⋅ L ⋅ C–1)}
(EQ. 41)
C_C
=
---------------V-----^I-^N------^â‹---⁽--2-----^â‹---^π-----^â‹---f--^H----^F-----^â‹-------L-----^â‹---C----^–----1----⁾---------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 41, R_FB is selected arbitrarily. The remaining
compensation components are then selected.
In Equation 41, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the
peak-to-peak sawtooth signal amplitude, as described in the
“Electrical Specifications” on page 13.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
35
FN6520.3
October 8, 2010