ISL6333_14 Datasheet, PDF (17/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
RSET
Connect this pin to VCC through a resistor to set the effective
value of the internal R_ISEN current sense resistors. It is
recommended a 0.1µF ceramic capacitor be placed in
parallel with this resistor for noise immunization.
OFS
The OFS pin provides a means to program a DC current for
generating an offset voltage across the resistor between FB
and VSEN. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.
ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, and
ISEN3+
These pins are used for differentially sensing the
corresponding channel output currents. The sensed currents
are used for channel balancing, protection and load line
regulation.
Connect ISEN1-, ISEN2-, and ISEN3- to the node between
the RC sense elements surrounding the inductor of their
respective channel. Tie the ISEN+ pins to the VCORE side
of their corresponding channel’s sense capacitor.
Tying ISEN3- to VCC programs the part for two-phase
operation.
UGATE1, UGATE2, and UGATE3
Connect these pins to their corresponding upper MOSFET
gates through 1.8Ω resistors. These pins are used to control
the upper MOSFETs and are monitored for shoot-through
prevention purposes.
BOOT1, BOOT2, and BOOT3
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to appropriately
chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC pin provides the necessary
bootstrap charge.
PHASE1, PHASE2, and PHASE3
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
LGATE1, LGATE2, and LGATE3
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
SS
A resistor, R_SS, placed from SS to ground or VCC, will set
the soft-start ramp slope. Refer to Equations 20 and 21 for
proper resistor calculation.
On the ISL6333 and ISL6333B the SS pin also determines
what voltage level the internal LDO regulates the BYP1 pin
to when PSI# is low. Tying the R_SS resistor to ground
regulates BYP1 to 5.75V. Tying the R_SS resistor to VCC,
regulates BYP1 to 7.75V.
VR_RDY
VR_RDY indicates whether VDIFF is within specified
overvoltage and undervoltage limits after a fixed delay from
the end of soft-start. It is an open-drain logic output. If VDIFF
exceeds these limits, an overcurrent event occurs, or if the
part is disabled, VR_RDY is pulled low. VR_RDY is always
low prior to the end of soft-start.
PSI#
The PSI# pin is a digital logic input pin used to indicate
whether the controllers should be in a low power state of
operation or not. When PSI# is HIGH the controllers will run in
it’s normal power state. When PSI# is LOW the controllers will
change their operating state to improve light load efficiency.
The controllers resume normal operation when this pin is
pulled HIGH again.
CPURST_N (ISL6333B, ISL6333C Only)
The CPURST_N pin is a digital logic input pin used in
conjunction with the PSI# pin to indicate whether the
ISL6333B and ISL6333C should be in a lower power state of
operation or not. If CPURST_N is high, the operating state of
the controllers can be changed to improve light load efficiency
by setting PSI# low. If CPURST_N is low, the controllers
cannot be put into it’s light load operating state. Once
CPURST_N toggles high again, there is a 50ms delay before
the controllers are allowed to enter a low power state.
Operation
Multi-phase Power Conversion
Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
solution. Designing a regulator that is cost-effective, thermally
sound, and efficient has become a challenge that only multi-
phase converters can accomplish. The ISL6333 family of
controllers help simplify implementation by integrating vital
functions and requiring minimal external components. The
block diagrams provide a top level view of multi-phase power
conversion using the ISL6333 family of controllers.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out-of-phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency 3x greater than the ripple frequency
of any one phase. In addition, the peak-to-peak amplitude of
the combined inductor currents is reduced in proportion to the
number of phases (Equations 1 and 2). Increased ripple
frequency and lower ripple amplitude mean that the designer
can use less per-channel inductance and lower total output
capacitance for any performance specification.
17
FN6520.3
October 8, 2010